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US 6,477,105 B2Granted
Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKengo Aritomi, Mikio Asakura, Takashi Ito, Kiyohiro Furutani
Life of this patent
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Abstract
Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.
Claims11
A semiconductor memory device, comprising:
- a plurality of memory cells arranged in rows and columns;
- and
- a plurality of sub-word lines provided corresponding to the rows of memory cells and having the memory cells of corresponding rows connected thereto, said plurality of sub-word lines divided into a plurality of blocks along a row direction and divided into groups by a prescribed number along a column direction;
- a plurality of main word lines provided in common to said plurality of blocks, extending in the row direction and corresponding to the respective groups of the sub-word lines;
- a main word line selecting circuit for driving an addressed main word line to a selected state according to a first address bit of a multi-bit address signal;
- a sub-decode circuit for generating complementary decode fast signals for designating a sub-word line within each group of said sub-word lines according to the multi-bit address signal excluding said first address bit;
- a sub-word line selecting circuit for generating complementary sub-word line select signals individually according to respective complementary decode fast signals from said sub-decode circuit, said complementary sub-word line select signals formed via separate paths;
- and
- a plurality of sub-word line drive circuits provided corresponding to the sub-word lines for driving corresponding sub-word lines to a selected state according to signals on corresponding main word lines and said complementary sub-word line select signals.
6 more elements
A semiconductor memory device, comprising:
- a sub word line connecting to memory cells arranged on a row;
- a main word line arranged corresponding to said sub word line;
- a predecoder receiving an address signal and predecoding the address signal to produce first and second predecode signals;
- a word decoder receiving and decoding the first predecode signal to produce a sub word decode signal;
- a first sub decoder coupled to said word decoder and producing a first sub decode signal in response to said sub word decode signal, said first sub decoder receiving a first operating power supply voltage from a first power source for operation;
- a second sub decoder coupled to said word decoder and producing a second sub decode signal in response to said sub word decode signal, the second sub decoder receiving a second power supply voltage from a second power supply source different from said first power source for operation;
- a row decoder receiving and decoding the second predecode signal to produce a main word line selecting signal onto said main word line;
- and
- a sub word driver coupled to said main word line and the first and second sub decoder, for driving said sub word line to a selected state in accordance with the first and second sub decode signals and the main word line selecting signal.
6 more elements
Dependencies are inferred from the claim text.