US 6,477,103 B1Granted

Reprogrammable fuse and method of operating

AssigneeSilicon Storage Technology, Inc.

InventorsTam M. Nguyen, Hung Q. Nguyen, Thuc Bui, Sang Thanh Nguyen

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Abstract

A reprogrammable fuse has a pair of non-volatile memory cells differentially programmed. The pair of non-volatile memory cells are connected to a pair of bitlines and through a pair of switches to a precharging voltage. The switches are controlled by a precharging and equalization signal, which when activated, serves to precharge the bitlines. The charged bitlines are then connected to the pair of differentially programmed non-volatile memory cells and one of the bitlines is discharged faster than the other. The resultant output is taken from one of the bitlines.

Claims8

Dependent claims

A reprogrammable fuse comprising:

a first non-volatile memory cell of the type having a first terminal and a second terminal in a substrate with a channel therebetween, a floating gate for storing charges and overlying a first portion of said channel and capacitively coupled to said first terminal, and a control gate overlying a second portion of said channel and for removing charges stored on said floating gate;
a second non-volatile memory cell of the type having a first terminal and a second terminal in a substrate with a channel therebetween, a floating gate for storing charges and overlying a first portion of said channel and capacitively coupled to said first terminal, and a control gate overlying a second portion of said channel and for removing charges stored on said floating gate;
a first bitline connected to the second terminal of said first non-volatile memory cell;
a second bitline connected to the second terminal of said second non-volatile memory cell;
a word line commonly connected to said control gates of said first and second non-volatile memory cells;
a source line commonly connected to said first terminals of said first and second non-volatile memory cells;
a precharging and equalization circuit commonly connected to said second terminals of said first and second non-volatile memory cells;
and
an output terminal connected to one of said first or second bitlines for supplying an output signal indicative of the state of said fuse;
wherein said fuse is erased by supply erase voltages to said word line and said source line;
and
wherein said fuse is programmed by supplying programming voltages to said source line, word line, and said first bitline and said second bitline, wherein said fuse is programmed to one state when said floating gate of said first non-volatile memory cell stores more charges than said floating gate of said second non-volatile memory cell;
and wherein said fuse is programmed to another state when said floating gate of said first non-volatile memory cell stores less charges than said floating gate of said second non-volatile memory cell;
and
wherein the programmed state of said fuse is read by supplying a precharging voltage to said first and second bitlines and differentially sensing said first and second bitlines.

12 more elements

Dependencies are inferred from the claim text.

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Abstract

A reprogrammable fuse comprising:

a first non-volatile memory cell of the type having a first terminal and a second terminal in a substrate with a channel therebetween, a floating gate for storing charges and overlying a first portion of said channel and capacitively coupled to said first terminal, and a control gate overlying a second portion of said channel and for removing charges stored on said floating gate;
a second non-volatile memory cell of the type having a first terminal and a second terminal in a substrate with a channel therebetween, a floating gate for storing charges and overlying a first portion of said channel and capacitively coupled to said first terminal, and a control gate overlying a second portion of said channel and for removing charges stored on said floating gate;
a first bitline connected to the second terminal of said first non-volatile memory cell;
a second bitline connected to the second terminal of said second non-volatile memory cell;
a word line commonly connected to said control gates of said first and second non-volatile memory cells;
a source line commonly connected to said first terminals of said first and second non-volatile memory cells;
a precharging and equalization circuit commonly connected to said second terminals of said first and second non-volatile memory cells;
and
an output terminal connected to one of said first or second bitlines for supplying an output signal indicative of the state of said fuse;
wherein said fuse is erased by supply erase voltages to said word line and said source line;
and
wherein said fuse is programmed by supplying programming voltages to said source line, word line, and said first bitline and said second bitline, wherein said fuse is programmed to one state when said floating gate of said first non-volatile memory cell stores more charges than said floating gate of said second non-volatile memory cell;
and wherein said fuse is programmed to another state when said floating gate of said first non-volatile memory cell stores less charges than said floating gate of said second non-volatile memory cell;
and
wherein the programmed state of said fuse is read by supplying a precharging voltage to said first and second bitlines and differentially sensing said first and second bitlines.

12 more elements