Read-ahead electrically erasable and programmable serial memory
AssigneeSTMicroelectronics S.r.l.
InventorsPaola Cavaleri, Bruno Leconte, Sébastien Zink
Life of this patent
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Abstract
A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.
Claims36
A method for reading a binary word in a serial input/output memory comprising:
- upon reception of a partial read address, in which there are N least significant bits lacking from a complete read address, simultaneously reading P first bits of M words of the memory having the partial read address;
- upon reception of the complete read address, selecting P first bits of a word designated by the complete read address and delivering the P first bits at a serial output of the memory;
- reading P following bits of the word designated by the complete read address during delivery of P previous bits;
- and
- delivering the P following bits at the serial output of the memory when the P previous bits are delivered.
A method for reading data from a memory comprising:
- simultaneously reading P bits of M words of the memory having a partially received read address which is missing N least significant bits from a complete read address;
- selecting P bits, upon reception of the complete read address, of a word designated by the complete read address;
- outputting the P bits;
- reading P following bits of the word designated by the complete read address while outputting the P bits;
- and
- outputting the P following bits when the P bits are outputted.
An integrated circuit memory comprising:
- a reading circuit for simultaneously reading P bits of M words of the memory having a partially received read address in which N least significant bits are missing from a complete address;
- and
- a selection circuit for selecting the P bits, when the complete address is received, of the word designated by the complete address and outputting the P bits;
- the reading circuit reading P following bits of the word designated by the complete address while the P bits are being outputted, and the selection circuit outputting the P following bits when the P bits are outputted.
An integrated circuit serial input/output memory comprising:
- a serial output;
- a reading circuit for simultaneously reading P first bits of M words of the memory having a partially received read address in which N least significant bits are missing from a complete address;
- and
- a selection circuit for selecting the P first bits, when the complete address is received, of a word designated by the complete address and outputting the P first bits at the serial output of the memory;
- the reading circuit reading P following bits of the word designated by the complete address while the P first bits are being outputted, and the selection circuit outputting the P following bits at the serial output after the P first bits are outputted.
Dependencies are inferred from the claim text.