Dynamic random access memory array having segmented digit lines

A memory-cell array, comprising:

• several memory cells arranged in rows and columns, the memory cells in each row including an access terminal coupled to an associated word line, and the memory cells in each column being coupled between a respective first digit line and a respective second digit line, the second digit line being divided into first and second portions;
• a sense amplifier having first and second data terminals, the first data terminal being coupled to the first digit line;
• a first isolation device selectively coupling the first portion of the second digit line to the second data terminal of the sense amplifier;
• and
• a second isolation device selectively coupling the second portion of the second digit line to the second data terminal of the sense amplifier.

A memory-cell array, comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of first line portions, each column of memory cells including several first line portions with each memory cell in a respective column coupled to one of the first line portions associated with the column;
• a plurality of second line portions, each second line portion coupled to the memory cells in a respective column;
• a plurality of sense amplifiers with each sense amplifier being associated with a respective column of memory cells, each sense amplifier having a first data terminal coupled to the associated second line portion and having a second data terminal;
• and
• a plurality of isolation devices, each column of memory cells having several associated isolation devices, each isolation device in a respective column having a control terminal coupled to receive a respective control signal, a first signal terminal coupled to one of the several first line portions associated with the column, and a second signal terminal coupled to the first data terminal of the sense amplifier associated with the column, each isolation device coupling its first signal terminal to its second signal terminal in response to the associated control signal.

A memory-cell array, comprising:

• a plurality of memory cells arranged in rows and columns, each memory cell including an access terminal coupled to a word line associated with each row of memory cells, a data terminal, and a reference terminal;
• a plurality of sense amplifiers with each sense amplifier being associated with a respective column of memory cells, each sense amplifier having first and second data terminals, the sense amplifier being operable to sense a voltage differential between the first and second data terminals and drive the data terminals to voltage levels corresponding to complementary logic levels in response to the sensed voltage differential;
• a plurality of digit line portions, each column of memory cells including several digit line portions, each digit line portion positioned adjacent a plurality of memory cells in the column and the data terminal of each memory cell in a respective column coupled to the adjacent one of the digit line portions;
• a plurality of strap portions, each column of memory cells including several strap portions, each strap portion having an end adjacent one of the digit line portions in the column and an end adjacent the sense amplifier associated with the column;
• a plurality of cell plate lines, each column of memory cells including at least one cell plate line coupled to receive a reference voltage, each cell plate line positioned adjacent a number of memory cells in the column, and the reference terminal of each memory cell in a respective column coupled to the adjacent one of the cell plate lines;
• and
• a plurality of isolation devices, each column of memory cells having several first and second associated isolation devices, each first isolation device in a respective column coupled to receive a respective control signal and operable, in response to the control signal, to couple one of the digit line portions through the adjacent strap portion to the second data terminal of the associated sense amplifier, and each second isolation device associated with a respective column coupled to receive a respective control signal and operable, in response to the control signal, to couple one of the cell plate lines to the first data terminal of the associated sense amplifier.

A dynamic random access memory, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a control circuit coupled the control bus;
• a read/write circuit coupled to the data bus;
• and
• a memory-cell array, including,
• several memory cells arranged in rows and columns, the memory cells in each row including an access terminal coupled to an associated word line, and the memory cells in each column being coupled between a respective first digit line and a respective second digit line, the second digit line being divided into several portions,
• a sense amplifier having first and second data terminals, the first data terminal being coupled to the first digit line, and
• several first isolation devices, each first isolation device selectively coupling an associated portion of the second digit line to the second data terminal of the sense amplifier.

A computer system, comprising:

• a data input device;
• a data output device;
• and
• computing circuitry coupled to the data input and output devices, the computing circuitry including a dynamic random access memory that includes,
• an address bus,
• a control bus,
• a data bus,
• an address decoder coupled to the address bus,
• a control circuit coupled the control bus,
• a read/write circuit coupled to the data bus, and
• a memory-cell array, including,
• several memory cells arranged in rows and columns, the memory cells in each row including an access terminal coupled to an associated word line, and the memory cells in each column being coupled between a respective first digit line and a respective second digit line, the second digit line being divided into several portions,
• a sense amplifier having first and second data terminals, the first data terminal being coupled to the first digit line, and
• several first isolation devices, each first isolation device selectively coupling an associated portion of the second digit line to the second data terminal of the sense amplifier.

A method of sensing data stored in a memory-cell array having a plurality of memory cells arranged in rows and columns, each memory cell in a respective column coupled to one of several digit line portions associated with the column, and each memory cell in a column further coupled to a cell plate line associated with the column, the memory-cell array further including a number of sense amplifiers, one sense amplifier associated with each column and each sense amplifier including first and second data terminals and operable to drive the data terminals to voltages corresponding to complementary logic levels in response to a voltage differential on the data terminals, the method comprising the steps of:

• activating a row of memory cells in the memory-cell array;
• transferring the data stored in each activated memory cell onto the respective digit line portion coupled to the activated cell;
• coupling each cell plate line to the first data terminal of the associated sense amplifier;
• coupling the digit line portion in each column that is coupled to the activated memory cell to the second data terminal of the associated sense amplifier;
• isolating each cell plate line from the first data terminal of the associated sense amplifier;
• isolating the digit line portion in each column that is coupled to the activated memory cell from the second data terminal of the associated sense amplifier;
• and
• coupling the digit lines coupled to the activated memory cells for a second time to the second data terminal of the respective sense amplifiers to thereby restore the sensed data in the activated memory cells.