Data backup memory
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorGenichiro Inoue
Life of this patent
Estimating the term…
Abstract
To provide a data backup memory that can function, when used to design an LSI, for a circuit operating at a frequency double that of a clock provided. The data backup memory includes a first precharge node, a second precharge node, a first precharge circuit, a second precharge circuit, a first discharge circuit, and a second discharge circuit. It can maintain and improve the characteristics of conventional data backup memories that the setup time therefor is ideally zero and that the worst value of a delay time can be designed to be small, while enabling data processing both at a rising and a falling edges of a clock signal.
Claims4
A data backup memory device using as input a timing control signal having a period indicating a first phase and a period indicating a second phase as well as a data signal that can assume a first state and a second state, to process said data signal synchronously with said timing control signal and temporarily store the state of said data signal, said data backup memory device comprising:
- a pulse signal generating circuit and at least one data backup memory, said data backup memory comprising:
- a first precharge node, a second precharge node, a first precharge circuit, a second precharge circuit, a first discharge circuit, and a second discharge circuit, wherein
- said pulse signal generating circuit for outputting a pulse signal having a first pulse potential period corresponding to a fixed period from a point of time of a change in said timing control signal from a first phase period to a second phase period and from a point of time of a change therein from said second phase period to said first phase period, and a second pulse potential period that is different from said first pulse potential period,
- said first precharge circuit for increasing a potential at said first precharge node up to and above a first boundary value during said second pulse potential period of said pulse signal,
- said first discharge circuit for reducing the potential at said first precharge node below the first boundary value while said input data signal is in the second state during the first pulse potential period of said pulse signal,
- said second precharge circuit for increasing a potential at said second precharge node up to or above a second boundary value while the potential at said first precharge node is below said first boundary value, and
- said second discharge circuit for reducing the potential at said second precharge node below said second boundary value while the potential at said first precharge node is equal to or above said first boundary value during the first pulse potential period of said pulse signal, the potential at said second precharge node being an output data signal.
Dependencies are inferred from the claim text.