Semiconductor memory device capable of detecting memory cell having little margin

A semiconductor memory device comprising:

• a memory cell array for inputting/outputting data;
• and
• a source voltage supplying circuit for supplying an internal source voltage for performing a sensing operation of amplifying read data read from a memory cell included in said memory cell array in response to a logic level of said read data,
• said memory cell array includes:
• a plurality of memory cells;
• a plurality of bit line pairs provided in correspondence with said plurality of memory cells;
• a plurality of equalizing circuits provided in correspondence with said plurality of bit line pairs, for equalizing said bit line pair to a precharge voltage;
• and
• a plurality of sense amplifiers provided in correspondence with said plurality of bit line pairs, for increasing a voltage on one of bit lines of said bit line pair to a memory array voltage and decreasing a voltage on the other of said bit line pair to a ground voltage in response to the logic level of said read data in said sensing operation,
• wherein in a normal operation mode, said source voltage supplying circuit supplies said internal source voltage directly to said memory cell array and, in a test mode, said source voltage supplying circuit supplies said internal source voltage to said memory cell array via an impedance.