Semiconductor memory and method of operating same
AssigneeFujitsu Limited
InventorsYoshiaki Okuyama, Shinya Fujioka, Waichiro Fujieda
Life of this patent
Estimating the term…
Abstract
An address signal is transmited to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, the decoder starts operating at an earlier timing of the operating cycle, outputting a decoding signal. This means reduction in access time. Moreover, the reception of a new address signal is inhibited after the activation of the control signal. This prevents the decoder from decoding incorrect address signals ascribable to noises and the like, thereby avoiding malfunctions.
Claims7
A semiconductor memory comprising:
- an address input circuit for transmitting an address signal to an internal circuit before activation of a control signal, and for inhibiting reception of a new address signal after the activation of said control signal;
- and
- a decoder for receiving said address signal transmitted from said address input circuit, for not operating decoding before the activation of said control signal, and for starting a decoding operation after the activation of said control signal.
A method of operating a semiconductor memory, comprising the steps of:
- transmitting an address signal to a decoder and not operating said decoder, before the activation of a control signal;
- and,
- inhibiting reception of a new address signal and starting a decoding operation of said decoder, after the activation of said control signal.
Dependencies are inferred from the claim text.