Method, apparatus, and system to enhance negative voltage switching
AssigneeIntel Corporation
InventorsKerry D. Tedrow, Rajesh Sundaram
Life of this patent
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Abstract
The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.
Claims30
A method, comprising:
- receiving a selection signal;
- receiving an erase-mode signal;
- determining a level-shifter signal from the selection signal and the erase mode signal;
- determining an inverter signal from the level-shifter signal and the selection signal;
- outputting the erase-mode signal in response to a first combination of the inverter signal and the level-shifter signal;
- and
- outputting a read-mode signal in response to a second combination of the inverter signal and the level-shifter signal.
An apparatus, comprising:
- a level shift stage circuit to output a level-shifter signal based upon a selection signal input and a negative charge pump input;
- an invert stage circuit to switch between the negative charge pump input and the selection signal input, based upon the selection signal input, to output as an inverter signal;
- and
- an output stage circuit to switch between a read-mode signal and the negative charge pump input based upon the inverter signal and the level-shifter signal.
An apparatus, comprising:
- a pull-up transistor having a gate coupled to a selection signal;
- a pull-down transistor coupled to said pull-up transistor, having a gate coupled to a bias input and a source/drain coupled to a negative charge pump;
- a first transistor having a drain/source coupled to the selection signal;
- a second transistor coupled to said first transistor, having a gate coupled to a drain/source of said pull-down transistor and a source/drain coupled to the negative charge pump;
- a read-mode transistor having a source/drain coupled to an output;
- and
- an erase-mode transistor having a drain/source coupled to the output and a source/drain coupled to the negative charge pump.
A system, comprising:
- a pull-up transistor having a gate coupled to a selection signal;
- a pulldown transistor coupled to said pull-up transistor, having a gate coupled to a bias input and a source/drain coupled to a negative charge pump;
- a first transistor having a drain/source coupled to the selection signal;
- a second transistor coupled to said first transistor, having a gate coupled to a drain/source of said pull-down transistor and a source/drain coupled to the negative charge pump;
- a read-mode transistor having a source/drain coupled to an output;
- an erase-mode transistor having a drain/source coupled to the output and a source/drain coupled to the negative charge pump;
- and
- a memory cell coupled to the output.
Dependencies are inferred from the claim text.