Nonvolatile semiconductor memory circuit capable of high-speed data reading

A nonvolatile semiconductor memory having a plurality of memory cell arrays, each of the memory cell arrays comprising:

• a cell bias circuit supplying a first voltage;
• a memory cell array having a plurality of memory cell transistors, a plurality of word lines, a plurality of drain lines disposed perpendicular to the word lines and a plurality of source lines disposed perpendicular to the word lines;
• a plurality of source line equalizing transistors connected between said cell bias circuit and the source lines, respectively, said source line equalizing transistors turning on when the memory cell is not selected;
• a plurality of drain line equalizing transistors connected between said cell bias circuit and the drain lines, respectively, said drain line equalizing transistors turning on when the memory cell is not selected;
• a plurality of bit lines;
• a plurality of main source lines;
• a plurality of source line selecting transistors connected between said main source lines and the source lines, respectively, said source line selecting transistors turning off when the memory cell is not selected;
• a plurality of drain line selecting transistors connected between said bit lines and the drain lines, respectively, said drain line selecting transistors turning off when the memory cell is not selected;
• a detecting circuit connected to said bit lines for supplying the first voltage to said bit lines for detecting data stored in the memory cells.