Usage of word voltage assistance in twin MONOS cell during program and erase

A method of single cell erase of a nonvolatile memory structured from twin MONOS cells, comprising:

• a) biasing a bit line of a selected cell to be erased to a first positive voltage,
• b) biasing a control gate of said selected cell to be erased to a first negative voltage,
• c) biasing a word gate coupled to a selected word line to a second negative voltage,
• d) biasing said word gate coupled to an unselected word line to a fourth positive voltage,
• e) creating an electric field in an insulator under said control gate of said selected cell.

A method of improvement in program disturb of unselected cells during programming of a selected cell, comprising:

• a) selecting a left or right side to program within a selected cell,
• b) biasing a selected bit line to a first positive voltage,
• c) biasing a near adjacent bit line which is adjacent to said selected bit line to zero volts,
• d) biasing a far adjacent bit line which is adjacent on a far side of said selected cell to a second positive voltage,
• f) biasing a selected word line to a third positive voltage,
• g) biasing an unselected word line to a negative voltage,
• h) establishing a negative gate to source voltage of unselected cells.

A word line erase means for a nonvolatile memory structured from twin MONOS memory cells, comprising:

• a) a means for selecting twin MONOS memory cells to be erased,
• b) a means for inhibiting from erase unselected twin MONOS memory cells,
• c) a means for creating an electric field under a control gate of selected twin MONOS memory cells of sufficient magnitude to eject trapped electrons from an insulator into a channel region,
• d) a means for creating an electric field under said control gate of the selected twin MONOS memory cells of sufficient magnitude to inject holes from the junction edge of a channel region into a trap site under the control gate.

A single cell erase means for a nonvolatile memory structured from twin MONOS memory cells, comprising:

• a) a means for selecting a single cell of twin MONOS memory cells to be erased,
• b) a means for inhibiting from erase unselected twin MONOS memory cells,
• c) a means for creating an electric field under a control gate of said selected single cell of twin MONOS memory cells of sufficient magnitude to eject trapped electrons from an insulator into a channel region,
• d) a means for creating an electric field under said control gate of said single cell of twin MONOS memory cells of sufficient magnitude to inject holes into said insulator under the control gate.