US 6,477,080 B2 · Circuits and methods for a static random access memory using vertical transistors

Abstract

A memory cell. The memory cell has a flip-flop that includes a cross-coupled pair of inverters. The inverters each include a pair of complementary, vertical transistors. A gate contact interconnects the gates of the inverters and acts as the input of the inverter. A shunt interconnects a first source/drain region of the complementary transistors and acts as the output of the inverter. A first vertical, access transistor is also included. The first vertical, access transistor has a gate that is coupled to a word line, a first source/drain region that is coupled to the output of one of the inverters, and a second source/drain region that is coupled to a first bit line. A second vertical, access transistor is also provided. The second vertical, access transistor has a gate that is coupled to the word line, a first source/drain region that is coupled to the output of the other inverter, and a second source/drain region that is coupled to a second bit line.

Claims40

Dependent claims

A method for forming a memory cell, the method comprising:

forming vertical bars of semiconductor material on a surface of a semiconductor wafer, wherein the bars have vertically aligned first source/drain, body and second source/drain regions;
separating out individual pillars of semiconductor material from the vertical bars to form vertical transistors, each transistor being formed from a single pillar of semiconducting material;
coupling vertical transistors from adjacent bars with body regions of different conductivity types to form inverters, forming each inverter including:
interconnecting the gates of the vertical transistors with a gate contact, the gate contact acting as an input of the inverter;
interconnecting the first source/drain regions from the vertical transistors from adjacent bars with body regions of different conductivity types with a shunt, the shunt acting as an output of the inverter;
cross-coupling the inverters to form a flip-flop;
and
coupling vertical, access transistors to inputs/outputs of the flip-flops.

5 more elements

A method of forming a memory cell, comprising:

forming a flip-flop that includes a cross-coupled pair of inverters wherein forming each inverter includes:
forming a pair of complementary, vertical transistors, each transistor being formed from one of a pair of single pillars of semiconducting material;
interconnecting the gates of the inverter with a gate contact, the gate contact acting as an input of the inverter;
interconnecting the first source/drain regions of the complementary vertical transistors with a shunt, the shunt acting as an output of the inverter;
coupling a gate of a first vertical access transistor to a word line;
coupling a first source/drain region of the first vertical access transistor to the output of one of the inverters;
coupling a second source/drain region of the first vertical access transistor to a first bit line;
coupling a gate of a second vertical access transistor to the word line;
coupling a source/drain region of the second vertical access transistor to the output of the other inverter;
and
coupling a second source/drain region of the second vertical access transistor to a second bit line.

8 more elements

A method of forming a memory cell, comprising:

forming a flip-flop that includes a cross-coupled pair of inverters wherein forming each inverter includes:
forming a pair of complementary, vertical transistors, each transistor being formed from one of a pair of single pillars of semiconducting material;
interconnecting the gates of the inverter with a gate contact, the gate contact acting as an input of the inverter;
interconnecting the first source/drain regions of the complementary vertical transistors with a shunt, the shunt acting as an output of the inverter;
coupling a gate of a first vertical access transistor to a word line;
coupling a first source/drain region of the first vertical access transistor to the output of one of the inverters;
coupling a second source/drain region of the first vertical access transistor to a first bit line that is buried beneath the body of the first vertical access transistor;
coupling a gate of a second vertical access transistor to the word line;
coupling a source/drain region of the second vertical access transistor to the output of the other inverter;
and
coupling a second source/drain region of the second vertical access transistor to a second bit line that is buried beneath the body of the second vertical access transistor.

8 more elements

A method of forming a memory device, comprising:

forming a number of word lines and a number of bit lines that are disposed to form an array;
forming a number of memory cells addressably disposed at intersections of the word lines and bit lines, wherein forming each memory cell includes:
forming a flip-flop that includes a cross-coupled pair of inverters wherein forming each inverter includes:
forming a pair of complementary, vertical transistors, each transistor being formed from one of a pair of single pillars of semiconducting material;
interconnecting the gates of the inverter with a gate contact, the gate contact acting as an input of the inverter;
interconnecting the first source/drain regions of the complementary vertical transistors with a shunt, the shunt acting as an output of the inverter;
coupling a gate of a first vertical access transistor to a word line;
coupling a first source/drain region of the first vertical access transistor to the output of one of the inverters;
coupling a second source/drain region of the first vertical access transistor to a first bit line that is buried beneath the body of the first vertical access transistor;
coupling a gate of a second vertical access transistor to the word line;
coupling a source/drain region of the second vertical access transistor to the output of the other inverter;
and
coupling a second source/drain region of the second vertical access transistor to a second bit line that is buried beneath the body of the second vertical access transistor.

10 more elements

Dependencies are inferred from the claim text.

Circuits and methods for a static random access memory using vertical transistors

Life of this patent

Circuits and methods for a static random access memory using vertical transistors

Life of this patent

Abstract

Claims40