Ferroelectric memory device having a ferroelectric capacitor disposed on an extended active area

Abstract

Disclosed is a ferroelectric memory device, which prevents a potential difference across a ferroelectric capacitor from being occurred and minimizes a step to be induced during the fabrication of the capacitor. The memory device comprises a first switching transistor having its gate coupled to a positive wordline, and its source and drain coupled between a bitline and a first node respectively; a ferroelectric capacitor coupled between the first node and a plateline; and a second switching transistor having its gate coupled to a negative wordline, and its source and drain coupled to the first node and the plateline respectively. A second node at which the source of the second switching transistor and the plateline are contacted is formed on an active area locating between two adjacent negative wordlines; and the ferroelectric capacitor is formed on the active area. The active area is broadly formed to prevent a resistance of the second node from being occurred.

Dependencies are inferred from the claim text.