Back to results
US 6,477,074 B2Granted
Semiconductor memory integrated circuit having high-speed data read and write operations
AssigneesFujitsu Limited, Kabushiki Kaisha Toshiba
InventorsAkira Kikutake, Shinichiro Shiratake, Kuninori Kawabata
Life of this patent
Estimating the term…
Abstract
Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.
Claims16
A semiconductor memory comprising:
- read amplifier circuits for amplifying read-out data transferred from sense amplifiers;
- and
- write buffer circuits for driving write data to said sense amplifiers,
- wherein said read amplifier circuits are arranged adjacent to each other, or said write buffer circuits are arranged adjacent to each other.
1 more element
Dependencies are inferred from the claim text.