Method and apparatus for content addressable memory with a partitioned match line
AssigneeSwitchcore, AB
InventorsAnders Edman, Henrik Johansson
Life of this patent
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AssigneeSwitchcore, AB
InventorsAnders Edman, Henrik Johansson
Estimating the term…
The present invention provides a content addressable memory (CAM) circuit that includes at least one row of memory cells storing data to be subjected to search data for a compare operation, with the cells in each row being inter-connected by a match line. Each cell can, if the search data does not match the stored data, discharge the match line in an evaluation operation. According to the present invention, a match line is partitioned into a least two segments, each segment having a first unit for precharging and evaluating the match line segment and a second unit for determining the result of the evaluation operation. The compare operation of the second and any subsequent segments is performed and the corresponding matchline segment involved only if the result of the compare operation of the respective preceding segment indicates a data match.
In a content addressable memory comprising at least one row of memory cells, each memory cell in said row for storing data and including a comparator for comparing the data in said memory cell with search data selectively coupled to the memory cell and a match line connected to the memory cell to indicate whether the search data matched the data stored-in the memory cell, a row compare circuit for generating a result output that indicates when the data in each memory cell in said row matches the search data coupled thereto, comprising:
In a content addressable memory comprising at least one row of memory cells, each memory cell in said row for storing data and including a comparator for comparing the data in said memory cell with search data selectively coupled to the memory cell and a match line connected to the memory cell to indicate whether the search data matched the data stored in the memory cell, a row compare circuit for generating a result output that indicates when the data in each memory cell in said row matches the search data coupled thereto, comprising:
In a content addressable memory comprising at least one group of rows of memory cells, each memory cell in each said row for storing data and including a comparator for comparing the data in said memory cell with search data selectively coupled to the memory cell and a match line connected to the memory cell to indicate whether the search data matched the data stored in the memory cell, a row compare circuit for generating a result output that indicates when the data in each memory cell in each said row matches the search data coupled thereto, comprising:
In a content addressable memory comprising a plurality of rows of memory cells, each memory cell in each said row for storing data and including a comparator for comparing the data in said memory cell with search data selectively coupled to the memory cell and a match line connected to the memory cell to indicate whether the search data matched the data stored in the memory cell, a row compare circuit for generating a result output that indicates when the data in each memory cell in each said row matches the search data coupled thereto, comprising:
Dependencies are inferred from the claim text.