Low inductance chip with center via contact

A multi-layer ceramic capacitive device mounted to a circuit board having a plurality of contacts in a plurality of tows, said plurality of contacts within each of said plurality of rows having an alternating pattern of polarity, said device comprising:

• a plurality of first electrode plates with a plurality of vias located therein;
• a plurality of second electrode plates with a plurality of vias located therein, said pluralities of first and second electrode plates interleaved to form said capacitive device wherein said plurality of vias in said first electrode plates, said plurality of vias in said second electrode plates and said plurality of contacts on said circuit board are aligned;
• a plurality of first terminals corresponding to alternating ones of said plurality of contacts in each of said plurality of rows such that all of said first terminals have the same polarity;
• and
• a plurality of second terminals corresponding to alternating ones of said plurality of contacts in each of said plurality of rows such that all of said second terminals have the same polarity which opposes the polarity of said first terminals.