General purpose digital read channel architecture

A circuit for determining a bit sequence from an analog waveform representing the bit sequence, at least one other parameter associated with the analog waveform, and a clock signal synchronized with the bit sequence as represented by the analog waveform, the circuit comprising:

• at least one analog to digital converter receiving the analog waveform and the at least one other parameter, the at least one analog to digital converter being operative to convert a current amplitude of the analog waveform and the at least one other parameter into a current number and at least one other number respectively;
• a plurality of registers connected to the at least one analog to digital converter and operative to store separately the current number and the at least one other number respectively;
• a controller connected to the at least one analog to digital converter and the plurality of registers, and receiving the clock signal, the controller being operative to trigger the at least one analog to digital converter to convert the current amplitude of the analog waveform and to convert the at least one other parameter in response to the clock signal, and the controller also being operative to command the plurality of registers to update the current number and the at least one other number being stored after completion of the analog waveform conversion;
• and
• a read only memory having a plurality of bits selectable by an address for output, the read only memory being connected to the plurality of registers such that the current number and the at least one other number form the address, and the read only memory further being operative to output the bit sequence as selected by the addresses from the plurality of bits.