Pulse width modulation system and image forming apparatus having the pulse width modulation system

A pulse width modulation system comprising a pulse width modulation circuit for outputting a necessary pulse width modulation signal in response to an input signal, and control means for controlling the pulse width modulation circuit,

• wherein the control means has means for outputting a delay setting signal and a division number setting signal to the pulse width modulation circuit in accordance with a phase comparison result signal output from the pulse width modulation circuit, and
• the pulse width modulation circuit comprises:
• switch control means for executing a control to generate a clock start signal and an EVEN/ODD switch signal, on the basis of an input clock signal;
• delay setting means for providing predetermined amounts of delay to the clock start signal from the switch control means, on the basis of the delay setting signal from the control means, and generating a plurality of pulse width modulation signals;
• phase select means for selecting one of the plurality of pulse width modulation signals generated by the delay setting means, on the basis of the division number setting signal from the control means, and outputting the selected signal as a clock end signal;
• comparison means for comparing the clock end signal from the phase select means with the clock start signal and outputting the phase comparison result signal to the control means;
• select means for selecting a pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting means, on the basis of the data signal and the pulse start position signal which have been input;
• inverting means for inverting a polarity of the pulse width modulation signal candidate selected by the select means;
• and
• switch means for receiving the pulse width modulation signal candidate inverted by the inverting means and the pulse width modulation signal candidate selected by the second select means, selecting either the pulse width modulation signal candidate inverted by the inverting means or the pulse width modulation signal candidate selected by the second select means in accordance with the EVEN/ODD switch signal from the switch control means, and outputting the selected candidate as the pulse width modulation signal.

A pulse width modulation system comprising a pulse width modulation circuit which outputs a necessary pulse width modulation signal in response to an input signal, and control section which controls the pulse width modulation circuit,

• wherein the control section has a unit which outputs a delay setting signal and a division number setting signal to the pulse width modulation circuit in accordance with a phase comparison result signal output from the pulse width modulation circuit, and
• the pulse width modulation circuit comprises:
• a switch control section which executes a control to generate a clock start signal, an EVEN-side data signal, an ODD-side data signal, an EVEN-side pulse start position signal, an ODD-side pulse start position signal and an EVEN/ODD switch signal, on the basis of a clock signal, a data signal and a pulse start position signal which are input;
• a delay setting section which provides predetermined amounts of delay to the clock start signal from the switch control section, on the basis of the delay setting signal from the control section, and generates a plurality of pulse width modulation signals;
• a phase select section which selects one of the plurality of pulse width modulation signals generated by the delay setting section, on the basis of the division number setting signal from the control section, and outputs the selected signal as a clock end signal;
• a comparison section which compares the clock end signal from the phase select section with the clock start signal and outputs the phase comparison result signal to the control section;
• a first select section which selects an EVEN-side pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting section, on the basis of the EVEN-side data signal and the EVEN-side pulse start position signal generated from the switch control section;
• a second select section, provided in parallel to the first select section, which selects an ODD-side pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting section, on the basis of the ODD-side data signal and the ODD-side pulse start position signal generated from the switch control section;
• and
• a switch section which receives the EVEN-side pulse width modulation signal candidate selected by the first select section and the ODD-side pulse width modulation signal candidate selected by the second select section, selects either the EVEN-side pulse width modulation signal candidate or the ODD-side pulse width modulation signal candidate in accordance with the EVEN/ODD switch signal from the switch control section, and outputs the selected candidate as the pulse width modulation signal.

A pulse width modulation system comprising a pulse width modulation circuit which outputs a necessary pulse width modulation signal in response to an input signal, and control section which controls the pulse width modulation circuit,

• wherein the control section has a unit which outputs a delay setting signal and a division number setting signal to the pulse width modulation circuit in accordance with a phase comparison result signal output from the pulse width modulation circuit, and
• the pulse width modulation circuit comprises:
• a switch control section which executes a control to generate a clock start signal and an EVEN/ODD switch signal, on the basis of an input clock signal;
• a delay setting section which provides predetermined amounts of delay to the clock start signal from the switch control section, on the basis of the delay setting signal from the control section, and generates a plurality of pulse width modulation signals;
• a phase select section which selects one of the plurality of pulse width modulation signals generated by the delay setting section, on the basis of the division number setting signal from the control section, and outputs the selected signal as a clock end signal;
• a comparison section which compares the clock end signal from the phase select section with the clock start signal and outputs the phase comparison result signal to the control section;
• a select section which selects a pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting section, on the basis of the data signal and the pulse start position signal which have been input;
• an inverting section which inverts a polarity of the pulse width modulation signal candidate selected by the select section;
• and
• a switch section which receives the pulse width modulation signal candidate inverted by the inverting section and the pulse width modulation signal candidate selected by the second select section, selects either the pulse width modulation signal candidate inverted by the inverting section or the pulse width modulation signal candidate selected by the second select section in accordance with the EVEN/ODD switch signal from the switch control section, and outputs the selected candidate as the pulse width modulation signal.

A pulse width modulation system which outputs a pulse width modulation signal in response to a signal input from a successive photoelectric element strings, which is input such that the signal is divided into an ODD-side and an EVEN-side, comprising:

• a first select section which selects an EVEN-side pulse width modulation signal candidate from a plurality of pulse width modulation signals generated from a delay setting section, on the basis of an EVEN-side data signal and an EVEN-side pulse start position signal,
• a second select section which is provided in parallel to the first select section and selects an ODD-side pulse width modulation signal candidate from the plurality of pulse width modulation signals generated from the delay setting section, on the basis of an ODD-side data signal and an ODD-side pulse start position signal generated from a switch control section;
• and
• a switch section which receives the EVEN-side pulse width modulation signal candidate selected by the first select section and the ODD-side pulse width modulation signal candidate selected by the second select section, selects either the EVEN-side pulse width modulation signal candidate or the ODD-side pulse width modulation signal candidate in accordance with the EVEN/ODD switch signal from the switch control section, and outputs the selected candidate as the pulse width modulation signal.

A method for outputting a pulse width modulation signal of a pulse width modulation system comprising a pulse width modulation circuit which outputs a necessary pulse width modulation signal in response to an input signal, and a control section which controls the pulse width modulation circuit,

• wherein the control section outputs a delay setting signal and a division number setting signal to the pulse width modulation circuit in accordance with a phase comparison result signal output from the pulse width modulation circuit, and
• the pulse width modulation circuit
• generates a clock start signal, an EVEN-side data signal, an ODD-side data signal, an EVEN-side pulse start position signal, an ODD-side pulse start position signal and an EVEN/ODD switch signal, on the basis of a clock signal, a data signal, and a pulse start position signal which are input,
• generates a plurality of pulse width modulation signals by providing the clock start signal with predetermined amounts of delay on the basis of the delay setting signal from the control section,
• selects one of the plurality of generated pulse width modulation signals on the basis of the division number setting signal from the control section, and outputs the selected signal as a clock end signal,
• compares the clock end signal with the clock start signal and outputs the phase comparison result signal to the control section,
• selects an EVEN-side pulse width modulation signal candidate from the plurality of generated pulse width modulation signals, on the basis of the EVEN-side data signal and the EVEN-side pulse start position signal which have been generated,
• selects an ODD-side pulse width modulation signal candidate from the plurality of generated pulse width modulation signals, on the basis of the ODD-side data signal and the ODD-side pulse start position signal which have been generated, and
• selects either the EVEN-side pulse width modulation signal candidate or the ODD-side pulse width modulation signal candidate in accordance with the EVEN/ODD switch signal, and outputs the selected candidate as the pulse width modulation signal.

A method for outputting a pulse width modulation signal of a pulse width modulation system comprising a pulse width modulation circuit which outputs a necessary pulse width modulation signal in response to an input signal, and a control section which controls the pulse width modulation circuit,

• wherein the control section outputs a delay setting signal and a division number setting signal to the pulse width modulation circuit in accordance with a phase comparison result signal output from the pulse width modulation circuit, and
• the pulse width modulation circuit
• generates a clock start signal and an EVEN/ODD switch signal on the basis of an clock signal which is input,
• generates a plurality of pulse width modulation signals by providing the clock start signal with predetermined amounts of delay on the basis of the delay setting signal from the control section,
• selects one of the plurality of generated pulse width modulation signals on the basis of the division number setting signal from the control section, and outputs the selected signal as a clock end signal,
• compares the clock end signal with the clock start signal and outputs the phase comparison result signal to the control section,
• selects a pulse width modulation signal candidate from the plurality of pulse width modulation signals that have been generated, on the basis of a data signal and a pulse start position signal which have been input,
• inverts a polarity of the pulse width modulation signal candidate which has been selected, and
• selects either the inverted pulse width modulation signal candidate or the selected pulse width modulation signal candidate in accordance with the EVEN/ODD switch signal, and outputs the selected candidate as the pulse width modulation signal.