Method and apparatus for adjusting video refresh rate in response to power mode changes in order to conserve power
AssigneeInternational Business Machines Corporation
InventorsSteven Edward Millman, Kevin Wilson Warren
Life of this patent
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Abstract
The present invention provides for a software routine executable by an image display system that controls at least one video timing signal (for example, the pixel clock signal) supplied to a display subsystem. More specifically, the software routine, adjusts the video timing signal in response to detection that the system is switching between power modes. The software routine preferably updates the video timing signal such that the system conserves power in response to detection that the system is switching from AC-powered operation to limited DC-powered operation.
Claims18
A program storage device for use in an image display system, said image display system having a Basic Input Output System (BIOS), a display subsystem that generates pixel data and a pixel clock signal for output to a display device, at least one control register, each containing a value to define a frequency of said pixel clock signal in accordance with a predefined mathematical equation, and a mechanism for detecting that the system is switching between power modes, the program storage device tangibly embodying a series of instructions executable by the system to perform method steps for controlling said pixel clock signal, the method steps comprising:
- in response to detection that the system is switching between power modes, adjusting said pixel clock signal by generating a new value for one or more of said at least one control register, wherein said generating a new value is not a selection of one or more values pre-stored in said BIOS.
A program storage device for use in an image display system having a display subsystem that generates pixel data and a pixel clock for output to a display device and a mechanism for detecting that the system is switching between power modes, the program storage device tangibly embodying a series of instructions executable by the system to perform method steps for controlling said pixel clock, the method steps comprising:
- in response to detection that the system is switching between power modes, adjusting said pixel clock signal,
- wherein said adjusting step updates said pixel clock signal such that the system conserves power in response to detection that the system is switching from AC-powered operation to limited DC-powered operation by reducing a frequency of said pixel clock signal, or such that the system leaves a power conserving mode in response to detection that the system is switching from limited DC-powered operation to AC-powered operation by increasing the frequency, wherein the frequency of said pixel clock signal is controlled by said subsystem using a numerical value stored in at least one control register to calculate a value for the frequency in accordance with a predefined mathematical equation, and wherein said adjusting step updates the frequency of the pixel clock signal by calculating a new value for said numerical value.
An image display system comprising:
- a Basic Input Output System (BIOS) embedded in a Read Only Memory ROM;
- a display subsystem that generates pixel data and a pixel clock signal for output to a display device, said display subsystem having at least one control register, each containing a value to define a frequency of said pixel clock signal in accordance with a predefined mathematical equation;
- means for detecting that the system is switching between power modes;
- and
- a program storage device tangibly embodying a series of instructions executable by the system to perform method steps for controlling said pixel clock signal, the method steps comprising, in response to detection that the system is switching between power modes, adjusting a value for a parameter controlling said pixel clock signal, wherein said adjusting does not comprise or result in a selection of one or more values stored in said BIOS to be loaded into one or more of said at least one control register.
An image display system comprising:
- a display subsystem that generates pixel data and a pixel clock signal for output to a display device;
- means for detecting that the system is switching between power modes;
- and
- a program storage device tangibly embodying a series of instructions executable by the system to perform method steps for controlling said pixel clock signal, the method steps comprising, in response to detection that the system is switching between power modes, adjusting said pixel clock signal,
- wherein the adjusting step updates said pixel clock signal such that the system conserves power in response to detection that the system is switching from AC-powered operation to limited DC-powered operation or that the system terminates a power conservation mode in response to detection that the system is switching from said limited DC-powered operation to AC-powered operation, wherein the adjusting step updates the frequency of said pixel clock signal, wherein the frequency of said pixel clock signal is controlled by a numerical value stored in at least one control register, said numerical value used by said display subsystem to calculate said frequency in accordance with a predefined mathematical equation, and wherein the adjusting step updates the frequency of the pixel clock signal by calculating a new value for said numerical value stored in said at least one control register.
Dependencies are inferred from the claim text.