Display device and a driver circuit thereof

A driver circuit for a display device comprising:

• a shift register circuit having a register circuit including a clocked inverter circuit and an inverter circuit connected in series;
• a digital data latch circuit having a first N-channel transistor and a second N-channel transistor in which the sources or drains are connected in series, a P-channel transistor, and a digital data holding circuit, wherein:
• a gate electrode of said second N-channel transistor is connected to the output line of said register circuit, a source or a drain of said second N-channel transistor is connected to a source or a drain of said first N-channel transistor, and the other end of the source or the drain of the said second N-channel transistor is connected to said digital data holding circuit;
• a gate electrode of said first N-channel transistor is connected to the output line of a register circuit neighboring said register circuit and the other end of the source or the drain of said first N-channel transistor is connected to a signal line to which digital data are inputted;
• and
• a gate electrode of said P-channel transistor is connected to a signal line to which a reset signal is inputted and one end of a source or a drain of said P-channel transistor is connected to a first power source whereas the other end of the source or the drain of the P-channel transistor is connected to said digital data holding circuit.

A driver circuit for a display device comprising:

• a shift register circuit having a plurality of register circuits including a clocked inverter circuit and an inverter circuit connected in series;
• a plurality of digital data latch circuits having a first P-channel transistor and a second P-channel transistor in which the sources or drains are connected in series, an N-channel transistor, and
• a digital data holding circuit, wherein:
• said clocked inverter circuit and said inverter circuit generate a timing signal on the basis of a clock signal, a clock back signal, and a start pulse inputted from outside and feeds the timing signal to a register circuit neighboring said register circuit and to a gate electrode of said second P-channel transistor;
• said N-channel transistor feeds a second electric current voltage to said digital data holding circuit in accordance with a reset signal that is inputted from outside to a gate electrode of said N-channel transistor;
• said first P-channel transistor takes in digital data inputted on the basis of said timing signal and feeds the digital data to the source or the drain of said second P-channel transistor;
• and
• the timing signal outputted from a register circuit neighboring said register circuit is fed to a gate electrode of said first P-channel transistor.

A driver circuit for a display device comprising:

• a shift register circuit having a register circuit including a clocked inverter circuit and an inverter circuit connected in series;
• a digital data latch circuit having a first P-channel transistor and a second P-channel transistor in which the sources or drains are connected in series, an N-channel transistor, and
• a digital data holding circuit, wherein:
• a gate electrode of said second P-channel transistor is connected to the output line of said register circuit, a source or a drain of said second P-channel transistor is connected to a source or a drain of said first P-channel transistor, and the other end of the source or the drain of the said second P-channel transistor is connected to said digital data holding circuit;
• a gate electrode of said first P-channel transistor is connected to the output line of a register circuit neighboring said register circuit and the other end of the source or the drain of said first P-channel transistor is connected to a signal line to which digital data are inputted;
• and
• a gate electrode of said N-channel transistor is connected to a signal line to which a reset signal is inputted and one end of a source or a drain of said N-channel transistor is connected to a second power source whereas the other end of the source or the drain of the N-channel transistor is connected to said digital data holding circuit.