Signal processing system employing two bit ternary signal

A signal processing system in which a differentially quantized digital signal is used,

• said digital signal being a ternary signal having two bits which represent only three values, of which one value is zero and the other two values represent a positive value and a negative value respectively,
• said system including a quantizer having:
• an input for receiving an analogue signal;
• first and second outputs;
• and
• first and second comparators having respective outputs coupled to said first and second outputs,
• respective first inputs each coupled to said input for receiving said analogue signal, and respective second inputs one receiving a reference level of half said positive value, and the other receiving a reference level of half said negative value,
• each comparator producing a binary indication of whether said analogue signal is more positive or more negative than the reference level applied to its second input, thereby to produce said ternary signal.

A signal processing system in which a differentially quantized digital signal is used,

• said digital signal being a ternary signal having two bits which represent only three values, of which one value is zero and the other two values represent a positive value and a negative value respectively;
• the system having an input for receiving said two bits of said ternary signal in parallel and a signal processor for processing said ternary signal;
• wherein said signal processor comprises a coefficient multiplier for multiplying said ternary signal by an n-bit coefficient, where n is greater than one, to produce an n bit product;
• and a requantiser for requantising said n-bit product as a ternary signal;
• and
• said requantizer selects the two most significant bits of said n bit signal product and inverts the most significant of said selected bits.

A signal processing system in which a differentially quantized digital signal is used,

• said digital signal being a ternary signal having two bits which represent only three values, of which one value is zero and the other two values represent a positive value and a negative value respectively,
• the system having an input for receiving said two bits of said ternary signal in parallel and a signal processor for processing said ternary signal;
• wherein said signal processor comprises a coefficient multiplier for multiplying said ternary signal by an n-bit coefficient where n is greater than one to produce an n bit product;
• and,
• said multiplier comprises, for each of said n bits of said coefficient, an Exclusive −OR gate having a first input for receiving said bit of said coefficient and a second input for receiving one of said bits of said ternary signal, and an AND gate having a first input for receiving the output of said Exclusive −OR gate and a second input for receiving an Exclusive −NOR combination of said two bits of said ternary signal.