Digital to analog converter
AssigneeADC Telecommunications Israel Ltd.
InventorsAharon M. Agizim, David Rouchbach, Zadok Rachamim
Life of this patent
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Abstract
A digital to analog converter is provided. The converter includes a multi-bit counter, a first and a second plurality of logic gates coupled to the multi-bit counter, a digital input selectively coupled to the first and second plurality of logic gates. The converter further includes a first AND gate coupled to an output of the first plurality of logic gates and a second AND gate coupled to an output of the second plurality of logic gates. In addition, the converter includes a clock coupled to an input of the first and second AND gates and an input of the multi-bit counter and a filter coupled to an output of the first and second AND gates, wherein the filter includes an output for an analog signal based on the digital input.
Claims55
A digital to analog converter, comprising:
- a multi-bit counter;
- a first and a second plurality of logic gates coupled to the multi-bit counter;
- a digital input selectively coupled to the first and second plurality of logic gates;
- a first AND gate coupled to an output of the first plurality of logic gates;
- a second AND gate coupled to an output of the second plurality of logic gates;
- a clock coupled to an input of the first and second AND gates and an input of the multi-bit counter;
- and
- a filter coupled to an output of the first and second AND gates, wherein the filter includes an output for an analog signal based on the digital input.
A digital to analog converter, comprising:
- a multi-bit counter;
- a first plurality of AND logic gates coupled to the multi-bit counter;
- a second plurality of AND logic gates coupled to the multi-bit counter;
- a digital input selectively coupled to the first and second plurality of AND logic gates;
- a first OR logic gate coupled to an output of the first plurality of AND logic gates;
- a second OR logic gate coupled to an output of the second plurality of AND logic gates;
- a first AND logic gate coupled to an output of the first OR logic gate;
- a second AND logic gate coupled to an output of the second OR logic gate;
- a clock coupled to an input of the first and second AND logic gates and an input of the multi-bit counter;
- a filter coupled to an output of the first and second AND logic gates;
- and
- an analog output coupled to the filter, wherein the analog output is based on the digital input.
A method of converting a multi-bit digital input signal to an analog signal, the method comprising:
- receiving a digital number;
- converting the digital number to a series of pulses;
- summing the series of pulses, wherein the pulses in a predetermined period represents the received digital number;
- and
- applying a clock signal to the sum of the series of pulses to obtain an analog signal that represents the digital number.
A digital to analog converter, comprising:
- a multi-bit counter;
- a plurality of logic circuits coupled to the multi-bit counter;
- a digital input selectively coupled to the plurality of logic circuits;
- a plurality of AND gates, each AND gate coupled to an output of one of the plurality of logic circuits;
- a clock signal coupled to an input of each of the plurality of AND gates;
- and
- a filter coupled to an output of each of the plurality of AND gates, wherein the filter includes an output for an analog signal based on the digital input.
A multi-bit digital to analog converter, comprising:
- a multi-bit counter;
- a clock coupled to an input of the multi-bit counter;
- an inverter coupled to an output of the multi-bit counter;
- a first and a second parallel-in, serial-out shift register each coupled to an output of the multi-bit counter;
- a digital input selectively coupled to the first and second shift registers;
- a first clock inverter coupled to an output of the clock;
- a second clock inverter coupled to an output of the clock;
- a first AND gate coupled to an output of the first clock inverter and an output of the first shift register;
- a second AND gate coupled to an output of the second clock inverter and the second shift register;
- a first resistor coupled to an output of the first AND gate;
- a second resistor coupled to an output of the second AND gate;
- wherein the first and second resistors are coupled to an analog output that is based on the digital input.
A method of testing a multi-bit digital to analog converter, the method comprising:
- generating an 8-bit digital number using the four most significant bits and four least significant bits of an analog to digital converter output;
- applying the four most significant bits to a plurality of inputs of a first 16-bit parallel-in, serial-out shift register;
- applying the four least significant bits to a plurality of inputs of a second 16-bit parallel-in, serial-out shift register;
- converting the four most significant bits to a first series of pulses;
- converting the four least significant bits to a second series of pulses;
- summing the first series of pulses, wherein the first series of pulses represents the digital equivalent of the 4 most significant bits received;
- summing the second series of pulses, wherein the second series of pulses represents the digital equivalent of the 4 least significant bits received;
- applying a clock signal to the sum of the first series of pulses to obtain an first analog signal that represents the digital equivalent of the 4 most significant bits;
- applying the clock signal to the sum of the second series of pulses to obtain a second analog signal that represents the digital equivalent of the 4 least significant bits;
- combining the first and second analog signals so as to produce a third analog signal that represents the 8-bit digital number;
- and
- comparing the third analog output to an output of an 8-bit digital to analog converter.
Dependencies are inferred from the claim text.