Block interleave circuit
AssigneeNEC Corporation
InventorNaoki Mitsutani
Life of this patent
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Abstract
By a shift register, n×d bits of data input Din are converted into parallel signals and latched by a register. A shift register is loaded with the parallel signals latched to the register when a data load signal is at high level and converts the loaded parallel signals into serial signals and outputs the serial signals as output data Dout when the data load signal is at low level. Therefore, connection between the register and the shift register is set such that a time-sequential order of the input data Din can be switched and accordingly, block interleaving can be carried out without using storages.
Claims7
A block interleave circuit for segmenting a constant amount of data in input data into one block and converting a time-sequential order of data in the block, said block interleave circuit comprising:
- serial/parallel conversion means for converting the constant amount of the data in the input data into parallel signals by using a first shift register and a register;
- and
- parallel/serial conversion means for converting the time-sequential order by inputting the parallel signals generated by the serial/parallel conversion means in a previously set order and successively shifting the parallel signals by using a second shift register.
Dependencies are inferred from the claim text.