Distributed balanced frequency multiplier
AssigneeFujitsu Quantum Devices Limited
InventorHideyuki Uchino
Life of this patent
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AssigneeFujitsu Quantum Devices Limited
InventorHideyuki Uchino
Estimating the term…
A branching section provides a fundamental input wave signal SI of a frequency f to the gate of a FET 15A having a grounded source and the source of a FET 15B having an AC grounded gate, and a signal joining section synthesizes the output signals of the FETs 15A and 15B. An open stub 24 as an amplitude attenuating element is connected to a transmission line 19B of the signal joining section. The length of the open stub 24 is not an integral multiple of λ/4, where λ denotes the wavelength of the fundamental signal SI, and adjusted in simulation such that an amplitude difference between second harmonics included in the drain voltage signals SD1 and SD2 of the respective FETs 15A and 15B is reduced to almost zero. Although the open stub 24 itself is a phase compensating element, since the transfer characteristic of the FET 15B changes by connecting the open stub 24 to the transmission line 19B, the open stub 24 works as an amplitude attenuating element.
A distributed balanced frequency multiplier comprising:
A method of fabricating a distributed balanced frequency multiplier, said distributed balanced frequency multiplier comprising:
Dependencies are inferred from the claim text.