Voltage level shifter and phase splitter

A voltage level shifter and phase splitter circuit comprising:

• an input signal;
• a first input inverter stage receiving said input signal and providing an inverted delayed out of phase signal to said input signal;
• a buffer stage receiving said input signal and providing a buffered delayed in phase signal to said input signal;
• said inverted delayed out of phase signal to said input signal and said buffered delayed in phase signal. to said input signal having approximately equal delay;
• a first constant current source coupled between said first input inverter stage and said buffer stage;
• a first output inverter stage coupled to said first constant current source and providing a voltage level shifted and out of phase signal to said input signal;
• a second constant current source coupled between said first input inverter stage and said buffer stage with an opposite polarity as said first constant current source;
• and
• a second output inverter stage coupled to said second constant current source and providing a voltage level shifted and in phase signal to said input signal;
• said voltage level shifted and out of phase signal to said input signal provided by said first output inverter stage and said voltage level shifted and in phase signal to said input signal provided said second output inverter stage being substantially balanced outputs.