Semiconductor device
AssigneeNEC Corporation
InventorKatsumi Yahiro
Life of this patent
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Abstract
A semiconductor device according to the invention is composed of a counter which outputs intermediate carry signals (CARRY 0, 1, 2) and the final carry signal (CARRY END) for determining the end of a delay output signal in a period starting from a delay pulse-generating trigger signal (DPT) and continuing for a predetermined time, and a delay circuit which outputs count up signals (COUNT UP) for counting up the counter on the basis of pulse signals generated in accordance with the intermediate carry signals and the DPT. According to the aforementioned semiconductor device, the delay output signal can be outputted without using an external clock signal.
Claims20
A semiconductor device, comprising:
- a counter which outputs a plurality of successive carry pulse signals in a period starting from an external input one pulse-generating trigger signal, continues for a predetermined time, and generates a final carry signal of said plurality of successive carry pulse signals for determining an end of a delay pulse output signal on a basis of said external input one pulse-generating trigger signal and said final carry signal of said plurality of successive pulse signals, and
- a delay circuit which outputs a plurality of count up signals to said counter on a basis of said plurality of successive carry pulse signals inputted from said counter and said external input one pulse-generating trigger signal.
A semiconductor device, comprising:
- a first counter which outputs a first plurality of successive carry pulse signals in a period starting from an external input one pulse-generating trigger signal, continues for a predetermined time, and generates a first carry end signal of said first plurality of successive carry pulse signals;
- a second counter which outputs a second plurality of successive carry pulse signals based on successive inputs of a plurality of first carry end signals and generates a second carry end signal of said second plurality of successive carry signals for determining an end of a delay pulse output signal which is derived from a period of said second carry end signal;
- and
- a delay circuit which outputs a plurality of count up signals to said first counter on a basis of input pulse signals corresponding to said first plurality of successive carry pulse signals and said second plurality of successive carry pulse signals, respectively, outputted from said first counter and said second counter and said external input one pulse-generating trigger signal.
A semiconductor device including a ring oscillator, comprising:
- an invertor located in a circuit path of the ring oscillator;
- a delay circuit that receives an output of the invertor, provides a plurality of count up signals, and is located in the circuit path of the ring oscillator;
- a counter that counts the plurality of count up signals in a period of time and is located in the circuit path of the ring oscillator, the period of time being determined by an initial delay pulse-generating trigger signal, which is received from outside the device, and a final carry signal, which is provided by the counter and corresponds to a predetermined count,
- wherein the initial external delay pulse-generating signal and the final carry signal provide timing signals for an outputted delay pulse, which is external to the circuit path of the ring oscillator.
A semiconductor device including a ring oscillator, comprising:
- an invertor located in a circuit path of the ring oscillator;
- a delay circuit that receives an output of the invertor, provides a plurality of count up signals and is located in the circuit path of the ring oscillator;
- a first counter that counts the plurality of count up signals in a first period of time and is located in the circuit path of the ring oscillator, the first period of time being determined by an initial external delay pulse-generating trigger signal, which is received from outside the device, and a first carry end signal, which is provided by the first counter and corresponds to a first predetermined count,
- a second counter that counts a plurality of first carry end signals, is external to the circuit path of the ring oscillator, and provides a second carry end signal that corresponds to a second predetermined count,
- wherein the initial external delay pulse-generating signal and the second carry end signal provide timing signals for an outputted delay pulse, external to the circuit path of the ring oscillator.
Dependencies are inferred from the claim text.