DLL circuit adjustable with external load
AssigneeFujitsu Limited
InventorYasurou Matsuzaki
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Abstract
The present invention provides a DLL circuit performing a phase adjustment in accordance to an output load, and capable of adjusting the phase in a shot time. In the present invention, in a delayed lock loop (DLL) circuit that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, the operating delay time of an output buffer is measured and the timing of the control clock is adjusted in accordance with this operating delay time. As a result, the timing of the output clock of the first variable delay circuit delay circuit is adjusted in accordance with the magnitude of the external load. This output clock or the output clock of a separate variable delay circuit subject to the same delay control is then utilized as a control clock.
Claims9
A delayed lock loop (DLL) circuit, connected to an output buffer, that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, in which the output buffer supplies an output signal to an output terminal in response to the control clock, said DLL circuit comprises:
- a first variable delay circuit that receives said reference clock and outputs the control clock and a first delayed clock delayed from the reference clock by a controlled delay time;
- a second variable delay circuit that receives the first delayed clock of said first variable delay circuit and outputs a second delayed clock delayed from the first delayed clock by a prescribed delay time;
- a phase comparison/delay control circuit that compares the phase of said reference clock and said second delayed clock and controls the amount of delay of said first variable delay circuit such that the phase of said reference clock and of the second delayed clock are in a prescribed relationship;
- and
- a delay measurement circuit that measures an operating delay time of said output buffer and sets the delay amount of said second variable delay circuit in accordance with the measured operating delay time.
Dependencies are inferred from the claim text.