Delay locked loop for use in synchronous dynamic random access memory
AssigneeHynix Semiconductor Inc.
InventorsSeong-Hoon Lee, Jung-Il Yang
Life of this patent
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Abstract
A delay locked loop (DLL) is used to compensate for a skew in a synchronous dynamic random access memory. The delay locked loop includes: a delay model for delaying an external clock signal by the skew to generate a delayed clock signal; a signal generation unit, in response to the external clock signal and the delayed clock signal, for generating control signals; a first delay unit, in response to the control signals, for delaying the delayed control signal to generate a first DLL clock signal, wherein the first delay unit has a large unit delay; and a second delay unit, in response to the control signals, for delaying the first DLL clock signal to generate a second DLL clock signal, wherein the second delay means in a small unit delay.
Claims11
A delay circuit for compensating for a skew in a synchronous dynamic random access memory, comprising:
- a delay model for delaying an external clock signal to generate a delayed clock signal;
- a signal generation means, responsive to the external clock signal and the delayed clock signal, for generating control signals, an internal clock signal, and a delayed internal clock signal;
- a first delay means, responsive to the control signals, for delaying the delayed internal clock signal to generate a first delay locked clock signal, wherein the first delay means has a first amount of delay time;
- and
- a second delay means, responsive to the control signals, for delaying the first delay locked clock signal to generate a second delay locked clock signal, wherein the second delay means has a second amount of delay time, the second amount of delay time being shorter than the first amount of delay time,
- wherein the signal generating means includes:
- a control means, response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signals include a shift signal, a replication signal and a replication enable signal;
- a first oscillation means, responsive to the internal clock signal and the delayed internal clock signal, for generating a measurement oscillating signal;
- and
- a second oscillation means, responsive to the replication signal and the replication enable signal, for generating a replication oscillating signal.
A delay circuit for compensating for a skew in a synchronous dynamic random access memory, comprising:
- a delay model for delaying an external clock signal to generate a delayed clock signal;
- a signal generation means for generating control signals, an internal clock signal, and a delayed internal clock signal in response to the external clock signal and the delayed clock signal, wherein the signal generation means includes first and second oscillators having the same configuration;
- a first delay means, responsive to the control signals and to first and second oscillation signals from the first and second oscillators, for delaying the delayed internal clock signal to generate a first delay locked clock signal, wherein the first delay means determines an amount of delay time using the first and second oscillation signals and generates a flag signal indicating a first locking;
- and
- a second delay means, responsive to the flag signal, the internal clock signal, the shift signal, and the first oscillation signal, for delaying the first delay locked clock signal to generate a second delay locked clock signal, wherein the second delay means has an amount of delay time smaller than the first delay means.
Dependencies are inferred from the claim text.