US 6,476,641 B2 · Low power consuming circuit

Abstract

A low power consuming circuit is provided which is capable of reducing power consumption by using a Vt (threshold voltage) characteristic of a MIS (Metal Insulator Semiconductor) transistor for generating a source voltage. N-channel transistors making up an inverter is configured by being stacked vertically. An N-channel transistor source voltage control circuit controls voltages so that a gate voltage of an N-channel transistor source voltage bias transistor existing in a lower state is transferred to a drain voltage terminal of the N-channel transistor source voltage bias transistor or to a supply voltage terminal.

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Drawings

Claims15

Dependent claims

A low power consuming circuit comprising:

a logic circuit containing, at least one inverter made up of a P-channel metal insulator semiconductor transistor and an N-channel metal insulator semiconductor transistor, both gates of which are connected to each other and both drains of which are connected to each other, and operating in an active mode and in a standby mode;
and
wherein a sub-threshold leakage current is reduced by boosting, in said standby mode, a threshold voltage in said P-channel and said N-channel metal insulator semiconductor transistors in said logic circuit by using a back gate bias effect induced by a source voltage control;
and
wherein a circuit to increase a source voltage used to boost said threshold voltage is made up of a source voltage control circuit having a complementary metal insulator semiconductor transistor and a source voltage bias transistor having a metal insulator semiconductor transistor whose gate is connected to a drain of said source voltage bias while in said standby mode.

2 more elements

A low power consuming circuit comprising:

a logic circuit containing, at least one inverter made up of a P-channel metal insulator semiconductor transistor and an N-channel metal insulator semiconductor transistor, both gates of which are connected to each other and both drains of which are connected to each other, and operating in an active mode and in a standby mode;
and
wherein a sub-threshold leakage current is reduced by boosting, in said standby mode, a threshold voltage in said P-channel and said N-channel metal insulator semiconductor transistors in said logic circuit by using a back gate bias effect induced by a source voltage control;
wherein a circuit to increase a source voltage used to boost said threshold voltage is made up of an N-channel transistor source voltage control circuit having a complementary metal insulator semiconductor transistor, a P-channel transistor source voltage control circuit having a complementary metal insulator semiconductor transistor, a first source voltage bias transistor having an N-channel metal insulator semiconductor transistors and a second source voltage bias transistor having a P-channel metal insulator semiconductor transistors;
wherein, in said logic circuit, a source of said N-channel metal insulator semiconductor transistor to be connected to a minimum power source is connected to a variable minimum potential line and a source of said P-channel metal insulator semiconductor transistor to be connected to a maximum power source in said logic circuit is connected to a variable maximum potential line;
wherein a gate of said first source voltage bias transistor is able to be switched to either of said maximum power source or a drain of said first source voltage bias transistor;
and
wherein a gate of said second source voltage bias transistor is able to be switched to either of said minimum power source or a drain of said second source voltage bias transistor.

5 more elements

Dependencies are inferred from the claim text.

Description7,637 words

Summary3,810 words

#1. Field of the Invention

#The present invention relates to a semiconductor integrated circuit made up of a CMIS (Complementary Metal Insulator Semiconductor) providing a low threshold voltage and more particularly to a low power consuming circuit enabling reduction in power consumption during standby (that is, while in a standby mode).

#The present application claims priority of Japanese Patent Application No. 2000-200643 filed on Jul. 3, 2000, which is hereby incorporated by reference.

Brief description of the drawings6 figures

#The above and other objects, advantages, and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:

#FIG. 1 is a circuit diagram showing configurations of a low power consuming circuit according to a first embodiment of the present invention;

#FIG. 2 is a circuit diagram showing configurations of a low power consuming circuit according to a second embodiment of the present invention;

Detailed description3,662 words

#Best modes of carrying out the present invention will be described in further detail using various embodiments with reference to the accompanying drawings.

#FIG. 1 is a circuit diagram showing configurations of a low power consuming circuit according to a first embodiment of the present invention. FIG. 1 shows an example of the low power consuming circuit in which a Vt controlled circuit is used as a CMIS standard inverter circuit for a low threshold logic circuit 3.

#The low threshold logic circuit 3 is made up of a P-channel MIS transistor 31 and an N-channel MIS transistor 32. A gate of the P-channel MIS transistor 31 is connected to a gate of the N-channel MIS transistor 32. A drain of the P-channel MIS transistor 31 is connected to a drain of the N-channel MIS transistor 32. The gates of the P-channel MIS transistor 31 and of the N-channel MIS transistor 32 are connected to an input terminal “IN” and the drains of the P-channel MIS transistor 31 and of the N-channel MIS transistor 32 are connected to an output terminal “OUT”.

Facts

Application

09/898,979Filed 3 Jul 2001

Priority

JP 2000-2006433 Jul 2000

Published

US 2001/0050379 A113 Dec 2001

Granted

5 Nov 2002

Term ended

3 Jul 2021

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification2 codes

G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
G11C
Static stores

Timeline

3 Jul 2000Priority claimedJP 2000-200643
3 Jul 2001Application filedUS 09/898,979
3 Jul 2001Assigned to NEC Corporationassignment of assignor's interest
13 Dec 2001PublishedUS 2001/0050379 A1
5 Nov 2002GrantedUS 6,476,641 B2
3 Mar 2003Assigned to NEC Electronics Corporationassignment of assignor's interest
13 Dec 2010Assigned to Renesas Electronics Corporationchange of name
3 Jul 2021Term endedEstimated

Low power consuming circuit

Life of this patent

Low power consuming circuit

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims15

Description7,637 words

Drawings

Classification2 codes

Life of this patent

Description7,637 words