Programmable number of metal lines and effective metal width along critical paths in a programmable logic device
AssigneeCypress Semiconductor Corporation
InventorsIrfan Rahim, John E. Berg
Life of this patent
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Abstract
A layout architecture for a programmable logic device comprising one or more adjacent metal lines, a first circuit, and a second circuit. The one or more adjacent metal lines may each comprise a critical path. The first circuit may be configured to present an input signal to each of the one or more adjacent metal lines in response to a configuration signal. The second circuit may be configured to (i) receive a signal from at least one of the one or more adjacent metal lines selected in response to the configuration signal and (ii) generate an output signal in response to the received signal.
Claims19
A layout architecture for a programmable logic device comprising:
- a plurality of adjacent metal lines comprising a critical path;
- a first circuit coupled to said plurality of adjacent metal lines and configured to present an input signal to each of said plurality of adjacent metal lines in response to a configuration signal;
- and
- a second circuit coupled to said plurality of adjacent metal lines and configured to (i) receive said input signal from at least one of said plurality of adjacent metal lines selected in response to said configuration signal and (ii) generate an output signal in response to said received signal, wherein said plurality of adjacent metal lines is configured to reduce a capacitance between each of said plurality of adjacent metal lines.
A method for providing a programmable effective metal line width in a programmable logic device comprising the steps of:
- (A) determining a critical path for said programmable logic device;
- (B) dedicating a plurality of adjacent metal lines along said critical path;
- (C) programming a first circuit to present an input signal to each of said plurality of adjacent metal lines of said critical path;
- (D) programming a second circuit to generate an output signal in response to a signal received from at least one of said plurality of adjacent metal lines;
- and
- (E) reducing a capacitance between each of said plurality of adjacent metal lines.
A layout architecture for a programmable logic device comprising:
- a plurality of adjacent metal lines comprising a critical path;
- a first circuit coupled to said plurality of adjacent metal lines and configured to present an input signal to each of said plurality of adjacent metal lines in response to a configuration signal;
- and
- a second circuit coupled to said plurality of adjacent metal lines and configured to (i) receive said input signal from at least one of said plurality of adjacent metal lines selected in response to said configuration signal and (ii) generate an output signal in response to said received signal, wherein said plurality of adjacent metal lines is configured to provide a predetermined effective metal line width.
A layout architecture for a programmable logic device comprising:
- a plurality-of adjacent metal lines comprising a critical path;
- a first circuit coupled to said plurality of adjacent metal lines and configured to present an input signal to each of said plurality of adjacent metal lines in response to a configuration signal;
- and
- a second circuit coupled to said plurality of adjacent metal lines and configured to (i) receive said input signal from at least one of said plurality of adjacent metal lines selected in response to said configuration signal and (ii) generate an output signal in response to said received signal, wherein said plurality of adjacent metal lines is configured to reduce a propagation delay of said input signal.
Dependencies are inferred from the claim text.