Method for testing signal paths between an integrated circuit wafer and a wafer tester
AssigneeFormFactor, Inc.
InventorsRalph G. Whitten, Benjamin N. Eldridge
Life of this patent
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AssigneeFormFactor, Inc.
InventorsRalph G. Whitten, Benjamin N. Eldridge
Estimating the term…
Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.
An apparatus for providing signal paths between ports of an integrated circuit (IC) tester and first test points arranged on an IC wafer when the IC tester is testing the IC wafer, and for enabling the IC tester to measure resistance of the signal paths when it is not testing the IC wafer, the apparatus comprising:
An apparatus for measuring resistance of signal paths within a interconnect structure for interconnecting ports of an integrated circuit (IC) tester with first test points arranged on an IC wafer to be tested, the apparatus comprising:
An apparatus for measuring resistance of signal paths within a interconnect structure for interconnecting ports of an integrated circuit (IC) tester with first test points arranged on an IC wafer to be tested, the apparatus comprising:
An apparatus for measuring resistance of signal paths within a interconnect structure for interconnecting ports of an integrated circuit (IC) tester with first test points arranged on an IC wafer to be tested, the apparatus comprising:
Dependencies are inferred from the claim text.