Semiconductor parallel tester
AssigneeTeradyne, Inc.
InventorArthur E. LeColst
Life of this patent
Estimating the term…
Abstract
A semiconductor parallel tester is disclosed for simultaneously testing a plurality of DUTs secured to a handling apparatus. The test system includes a system controller for initiating system test signals and a pin electronics assembly responsive to the system test signals to generate test pattern signals for application to the plurality of DUTs. The system further includes a signal interface defining a plurality of direct signal paths between the handling apparatus and the pin electronics assembly.
Claims10
A semiconductor tester for testing a plurality of DUTs secured to a handling apparatus, said tester includes:
- a system controller for initiating system test signals;
- a pin electronics assembly responsive to said system test signals for generating test pattern signals for application to said plurality of DUTs;
- and
- a signal interface adapted for defining a plurality of direct signal paths, when said tester is coupled to said handling apparatus, between said handling apparatus and said pin electronics assembly, the signal interface including,
- a substantially circular probe ring formed with a plurality of axially opening cavities, said cavities disposed in a spaced-apart annular configuration;
- and
- a plurality of modular harness assemblies, each of said plurality of modular harness assemblies including respective proximal and distal ends, said proximal end including a pogo module for nesting in one of said plurality of axially opening cavities and said distal end including at least one connector for engaging said pin electronics assembly.
A semiconductor tester for testing a plurality of DUTs secured to a handling apparatus, said tester includes:
- a system controller for initiating system test signals;
- a pin electronics assembly responsive to said system test signals for generating test pattern signals for application to said plurality of DUTs;
- and
- a signal interface adapted for defining a plurality of direct signal paths, when said tester is coupled to said handling apparatus, between said handling apparatus and said pin electronics assembly, the signal interface including,
- a substantially circular probe ring formed with a plurality of axially opening cavities, said cavities disposed in a spaced-apart annular configuration;
- and
- a plurality of modular harness assemblies, each of said plurality of modular harness assemblies including respective proximal and distal ends, said proximal end including a pogo module for nesting in one of said plurality of axially opening cavities, the pogo module formed with an array of closely spaced throughbores, each of said throughbores configured to receive a pogo pin assembly, the pogo pin assembly including
- a coaxial cable having a center conductor and a shield, said shield terminating at a distal end, and said center conductor projecting axially from said distal end and defining a distal tip;
- a pogo pin fixed in close-spaced axial relationship to said distal tip via a pogo receptacle;
- and
- an impedance compensation element coupled to said cable and pogo pin, and said distal end including at least one connector for engaging said pin electronics assembly.
A semiconductor tester for testing a plurality of DUTs secured to a handling apparatus, the handling apparatus having a device-interface-board coupled to the plurality of DUTs, the tester including:
- means for initiating system test signals;
- means, responsive to the system test signals, for generating test pattern signals for application to the plurality of DUTs;
- and
- means for interfacing the test pattern signals between the handling apparatus and the means for generating test pattern signals.
Dependencies are inferred from the claim text.