Ringing preventive circuit, device under test board, pin electronics card, and semiconductor device

A ringing preventive circuit, comprising:

• buffer amplifier having an input terminal and an output terminal;
• a first comparator having a first input terminal connected to said output terminal of said buffer amplifier, a second input terminal provided with a first reference voltage, and an output terminal, for outputting a first control signal from said output terminal in response to a result of comparison between voltages at said first and second input terminals;
• a first current supply circuit having a first terminal connected to a first power source for supplying a first voltage, a second terminal connected to said input terminal of said buffer amplifier, and a control signal input terminal connected to said output terminal of said first comparator, for controlling conduction and non-conduction of a current flowing from said first terminal to said second terminal as a function of said first control signal;
• a second comparator having a first input terminal connected to said output terminal of said buffer amplifier, a second input terminal provided with a second reference voltage, and an output terminal, for outputting a second control signal from said output terminal in response to a result of comparison between voltages at said first and second input terminals;
• a second current supply circuit having a first terminal connected to a second power source for supplying a second voltage, a second terminal connected to said input terminal of said buffer amplifier, and a control signal input terminal connected to said output terminal of said second comparator, for controlling conduction and non-conduction of a current flowing from said first terminal to said second terminal as a function of said second control signal;
• and
• an intermediate voltage generating circuit having an output terminal, for outputting an intermediate voltage of the output voltages of said first power source and said second power source from said output terminal of said intermediate voltage generating circuit,
• wherein said first current supply circuit, comprises:
• first switch means having a control electrode connected to said output terminal of said first comparator, a first current electrode connected to a first current mirror associated with said first power source, and a second current electrode connected to said output terminal of said intermediate voltage generating circuit, for controlling conduction and non-conduction of a current flowing between said first and second current electrodes in response to said first control signal applied to said control electrode,
• said first current mirror circuit having a first current output terminal connected to said first current electrode of said first switch means, and a second current output terminal connected to said input terminal of said buffer amplifier, for outputting a first current from said first current output terminal and a second current from said second current output terminal, said second current in said second current output terminal is duplicated in said first current output terminal,
• said second current supply circuit, comprises:
• second switch means having a control electrode connected to said output terminal of said second comparator, a first current electrode connected to a second current mirror associated with said second power source, and a second current electrode connected to said output terminal of said intermediate voltage generating circuit, for controlling conduction and non-conduction of a current flowing between said first and second current electrodes in response to said second control signal applied to said control electrode, and
• said second current mirror circuit having a first current output terminal connected to said first current electrode of said second switch means, and a second current output terminal connected to said input terminal of said buffer amplifier, for outputting a third current from said first current output terminal of said second current mirror circuit and a fourth current from said second current output terminal of said second current mirror circuit, said fourth current is duplicated in said first current output terminal of said second current mirror circuit.