Method and apparatus for testing high frequency delay locked loops
AssigneeLSI Logic Corporation
InventorRoger L. Roisen
Life of this patent
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Abstract
A delay-locked loop circuit is provided which includes a delay-locked loop, a delay element and a multiplexer. The delay-locked loop has a reference clock input, a feedback clock input and a clock output. The delay element has a delay input which is coupled to the clock output and a delay output. The multiplexer has a first multiplexer input which is coupled to the clock output, a second multiplexer input which is coupled to the delay output and a multiplexer output which is coupled to the feedback input.
Claims14
A delay-locked loop circuit comprising:
- a delay-locked loop having a reference clock input, a feedback clock input and a clock output;
- a delay element having a delay input coupled to the clock output and a delay output;
- and
- a multiplexer having a first multiplexer input coupled to the clock output, a second multiplexer input coupled to the delay output and a multiplexer output coupled to the feedback input.
A method of testing a delay-locked loop that is embedded within an integrated circuit, the method comprising:
- (a) applying a test clock to a reference clock input of the delay-locked loop, wherein the test clock signal has a frequency that is outside a normal locking range of the delay-locked loop;
- (b) lowering the normal locking range of the delay-locked loop to a test locking range, wherein the frequency of the test clock signal is within the test locking range;
- and
- (c) detecting a representation of an output clock signal generated by the delay-locked loop on a clock output of the delay-locked loop in response to the test clock signal when the delay-locked loop has the test locking range.
An integrated circuit comprising:
- an embedded delay-locked loop having a reference clock input, a feedback clock input, a test control input, a clock output and a feedback path from the clock output to the feedback clock input;
- and
- means for selectively changing a locking range of the delay-locked loop from a first frequency range to a second, slower frequency range as a function of a test control signal applied to the test control input.
Dependencies are inferred from the claim text.