Transistor which can minimize the DC resistance of the wiring and lead formed on a semiconductor chip

A semiconductor device comprising:

• a semiconductor chip which is comprised of:
• a plurality of transistor cells arranged on a rectangular substrate;
• a first electrode electrically connected to first type semiconductor regions of said plurality of transistor cells, on which a first electrode pad is formed;
• a second electrode electrically connected to second type semiconductor regions of said plurality of transistor cells, on which a second electrode pad is formed, and
• a third electrode electrically connected to third type semiconductor regions of said plurality of transistor cells, said third electrode being formed on a back surface of the rectangular substrate;
• a first lead connected to said first electrode pad;
• a second lead connected to said second electrode pad, and
• a third lead which has a rectangular island to die-bond said semiconductor chip and is extended out from a long side of said island in a perpendicular direction thereof,
• wherein said first electrode pad and said second electrode pad are formed on a side where a plurality of transistor cells are arranged, each of said first and second electrode pads being arranged at a different long side of the semiconductor chip opposed each other,
• further wherein said first and second leads are directly bonded onto said first and second electrode pads respectively.