Apparatus and manufacturing method for semiconductor device adopting NA interlayer contact structure

An interlayer contact structure in a semiconductor device, comprising:

• a stacked lower conductive layer pattern comprising a first doped silicon layer pattern and a first silicide layer pattern formed over the first doped silicon layer pattern;
• an insulating layer formed over the stacked lower conductive layer pattern;
• an opening formed in the insulating layer extending partially into the first silicide layer pattern, the opening having an undercut formed between the insulating layer and the first silicide layer pattern;
• and
• a stacked upper conductive layer patten comprising a second doped silicon layer pattern and a second silicide layer pattern formed over the second doped silicon layer pattern, wherein the second doped silicon layer pattern of the upper conductive layer directly contacts the first silicide layer pattern having the groove through the opening.

An interlayer contact structure in a semiconductor device, comprising:

• a stacked lower conductive layer pattern comprising a first doped silicon layer pattern and a first silicide layer pattern formed over the first doped silicon layer patten;
• a capping layer formed over the stacked lower conductive layer pattern, the capping layer being formed of an insulating material;
• an insulating layer formed over the capping layer and the stacked lower conductive layer pattern, the insulating layer formed of silicide glass and having a planarized surface;
• an opening formed in the insulating layer extending down to the first doped silicon layer pattern, the opening having an undercut formed between the insulating layer pattern and the first silicide layer pattern;
• and
• a stacked upper conductive layer pattern comprising a second doped silicon layer pattern and a second silicide layer pattern formed over the second doped silicon layer pattern, wherein the second doped silicon layer pattern of the upper conductive layer directly contacts the first doped silicon layer pattern through the opening.

An interlayer contact structure in a semiconductor device, comprising:

• a gate insulating layer;
• a stacked lower conductive layer pattern formed over the gate insulating layer, the stacked lower conductive layer comprising a first doped silicon layer pattern and a first silicide layer pattern formed over the first doped silicon layer pattern;
• a capping layer formed over the stacked lower conducive layer pattern;
• an insulating layer formed over the capping layer and the stacked lower conductive layer pattern, the insulating layer formed of silicate glass and having a planarized surface;
• an opening formed in the insulating layer extending down to the first doped silicon layer pattern, the opening having an undercut formed between the insulating layer pattern and the first silicide layer pattern;
• and
• a stacked upper conducive layer pattern comprising a second doped silicon layer pattern and a second silicide layer pattern formed over the second doped silicon layer pattern, wherein the second doped silicon layer pattern through the opening.

An interlayer contact structure in a semiconductor device, comprising:

• a stacked lower conductive layer pattern comprising a first doped silicon layer pattern and a first silicide layer pattern formed over the first doped silicon layer pattern;
• an insulating layer formed over the stacked lower conductive layer pattern;
• an opening formed in the insulating layer extending down to the first doped silicon layer pattern, the opening having an undercut formed between the insulating layer pattern and the first silicide layer pattern;
• and
• an upper doped silicon layer pattern formed on the insulating layer and directly contacting the first doped silicon layer pattern through the opening.

An interlayer contact structure in a semiconductor device, comprising:

• a stacked lower conductive layer pattern comprising a first doped silicon layer pattern and a first silicide layer pattern formed over the first doped silicon layer pattern;
• an insulating layer formed over the stacked lower conductive layer pattern;
• an opening formed in the insulating layer extending partially into the first silicide layer pattern, the opening having an undercut formed between the insulating layer and the first silicide layer pattern;
• and
• an upper doped silicon layer pattern formed on the insulating layer and directly contacting the first silicide layer pattern having the groove through the opening.