US 6,476,488 B1Granted

Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections

AssigneeVanguard International Semiconductor Corporation

InventorsErik S. Jeng, Bi-Ling Chen, Chien-Sheng Hsieh

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Abstract

A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N− contact areas. An N+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N+ and P+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N− contacts, while forming metal landing plugs to the N+ and P+ contacts. Via holes can now be etched in a second insulating layer over and to the landing plugs. The polysilicon landing plugs to the N− contacts reduce current leakage, while the metal contacts to the N+ and P+ contacts reduce the contact resistance (Rc). The landing plugs protect the substrate contacts from damage during via hole etch and reduce the aspect ratio for making more reliable contacts.

Claims5

Dependent claims

Polysilicon landing plugs and metal landing plugs with electrical interconnections for contacts on semiconductor integrated circuits comprised of:

a semiconductor substrate having device areas of a first type and device areas of a second type, and having devices with N− doped contacts in said device areas of said first type, and having N+ and P+ doped contacts in said device areas of said second type;
a conformal first etch-stop layer partially etched back to form sidewall spacers on said devices and to protect said device areas of said first type and said device areas of said second type;
a planar insulating layer over said device areas;
said planar insulating layer and said etch-stop layer having first openings self-aligned to said devices and said first openings over and to said N− doped contacts in said device areas of said first type;
an N+ doped polysilicon layer on said planar insulating layer and in said first openings and contacting said N− contacts;
said N+ doped polysilicon layer, said planar insulating layer, and said first etch-stop layer having second openings to said N+ and P+ contacts in said device areas of said second type;
interconnecting lines formed from a barrier layer, a metal layer, and a second etch-stop layer and from said N+ doped polysilicon layer, and concurrently leaving said N+ doped polysilicon landing plugs in said device areas of said first type and leaving said metal layer in said N+ and said P+ contacts in said device areas of said second type to form said metal landing plugs.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/696,086Filed 26 Oct 2000 · division
Priority: 11 Feb 1999
Granted: 5 Nov 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/0698
Of conductive parts of the interconnections: local interconnections
H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells