Chip-size integrated circuit package having slits formed in an insulator tape
AssigneeNEC Corporation
InventorsShohei Okazaki, Yoshihiro Matsumoto
Life of this patent
Estimating the term…
Abstract
In a chip-size package, an insulator tape is formed with a conductive wire having a wider section which is greater in width than other sections of the wire and a conductive bump connected to the wider section of the wire. The insulator tape is further formed with a first plurality of slits arranged on one side of the wider section of the wire and a second plurality of slits arranged on the other side of the wider section. An integrated circuit chip is provided having a conductive pad connected to the copper bump.
Claims18
A chip-size package comprising:
- an insulator tape having a conductive wire, the conductive wire having a wider section that is greater in width than other sections of the wire;
- a conductive bump connected to the wider section of the wire;
- and
- an integrated circuit chip having a conductive pad connected to said conductive bump,
- wherein the tape has a first plurality of slits arranged adjacent to a first side of the wider section of the wire and a second plurality of slits arranged adjacent to a second side of the wider section of the wire, the first plurality of slits and the second plurality of slits reducing the effects of deformation of the tape on the connection of the conductive bump to the conductive pad of the integrated circuit chip.
A method of fabricating a chip-size package comprising the steps of:
- forming a conductive wire on an insulator tape, said wire having a wider section that is greater in width than other sections of the wire, and the wire having a conductive bump connected to the wider section of the wire;
- forming, in said insulator tape, a first plurality of slits arranged adjacent to a first side of said wider section of the wire and a second plurality of slits arranged adjacent to a second side of the wider section of the wire;
- securing said insulator tape to an integrated circuit chip having a conductive pad thereon;
- and
- pressure contacting said conductive bump to said conductive pad while applying heat thereto,
- the first plurality of slits and the second plurality of slits reducing the effects of deformation of the tape on the connection of the conductive bump to the conductive pad of the integrated circuit.
Dependencies are inferred from the claim text.