Cavity semiconductor package with exposed leads and die pad

A semiconductor chip package comprising:

• a die pad having opposed top and bottom surfaces and being of a die pad thickness;
• a semiconductor die mounted to the top surface of the die pad and having at least one bond pad disposed thereon;
• a plurality of leads extending toward the die pad in substantially co-planar relation thereto, each of the leads being of a lead thickness which is substantially equal to the die pad thickness and having a body which defines opposed top and bottom surfaces and an inner end disposed in close proximity to the die pad;
• a package mold having a bottom surface and a cavity which is partially defined by an upper surface of a floor of the package mold, the floor having a floor thickness between the upper surface thereof and the bottom surface of the package mold which is substantially equal to the die pad and lead thicknesses;
• the package mold being formed such that the top surface of the die pad and portions of the top surfaces of the leads extending to the inner ends thereof are exposed within and substantially flush with the upper surface of the floor, and the bottom surfaces of the die pad and the leads are exposed within and substantially flush with the bottom surface of the package mold;
• and
• at least one conductor electrically connected to and extending between the bond pad of the semiconductor die and one of the leads, the conductor being contained within the cavity of the package mold.

A semiconductor chip package comprising:

• a die pad;
• a semiconductor die mounted to the die pad;
• a plurality of leads electrically connected to the semiconductor die, each of the leads being of a lead thickness, having a body which defines opposed top and bottom surfaces, and including a tab which extends outwardly from the body;
• and
• a package mold having a bottom surface and a cavity which is partially defined by an upper surface of a floor of the package mold, the floor having a floor thickness between the upper surface thereof and the bottom surface of the package mold which is substantially equal to the lead thickness;
• the package mold being formed such that portions of the top surfaces of the leads extending to the inner ends thereof are exposed within the cavity, the bottom surfaces of the leads are exposed within the bottom surface of the package mold, and each of the tabs is entirely encapsulated within the package mold.

A semiconductor chip package comprising:

• a die pad having opposed top and bottom surfaces and being of a die pad thickness;
• a semiconductor die mounted to the top surface of the die pad;
• a plurality of leads extending toward the die pad in substantially co-planar relation thereto, each of the leads being of a lead thickness and having a body defining opposed top and bottom surfaces and a curved inner end disposed in close proximity to the die pad, and including a tab extending outwardly from the body thereof;
• a package mold having opposed top and bottom surfaces, a first cavity which is partially defined by an upper surface of a floor of the package mold, and a second cavity adjacent the first cavity, the floor having a floor thickness between the upper surface thereof and the bottom surface of the package mold which is substantially equal to the die pad and lead thicknesses, the package mold being formed such that the semiconductor die, the top surface of the die pad, and portions of the top surfaces of the leads extending to the inner ends thereof are exposed within the cavity, the bottom surfaces of the die pad and the leads are exposed within the bottom surface of the package mold, and the tabs of the leads are completely encapsulated by the package mold;
• conductors electrically connected to and extending between the semiconductor die and respective ones of the leads, the conductors being contained within the first cavity;
• and
• a lid disposed within the second cavity and enclosing the first cavity.