Semiconductor device capable of enhancing a withstand voltage at a peripheral region around an element in comparison with a withstand voltage at the element
AssigneeDenso Corporation
InventorTakeshi Miyajima
Life of this patent
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AssigneeDenso Corporation
InventorTakeshi Miyajima
Estimating the term…
A semiconductor device has an element region including MOS structure. A p-well region, a connecting impurity diffused region, and an impurity diffused region for guard ring are formed in an n-type semiconductor layer so as to form a well region, The well region has a step defining a higher portion and a lower portion lower than the higher portion so that the impurity diffused region for guard ring is located at the lower portion. The lower portion is located at a periphery of the element region. In this structure, the impurity diffused region for guard ring is completely depleted while the connecting impurity diffused region is partially depleted so that a portion having carriers remains therein while a depletion layer expands in the connecting impurity diffused region before a breakdown due to a reverse bias occurs in the element region.
A semiconductor device comprising:
A semiconductor device comprising:
A semiconductor device comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.