Back to results
US 6,476,453 B2Granted
Semiconductor integrated circuit device having capacitor element
AssigneeHitachi, Ltd.
InventorsNaotaka Hashimoto, Yutaka Hoshino, Shuji Ikeda
Life of this patent
Estimating the term…
Abstract
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
Claims15
A semiconductor integrated circuit device, comprising:
- a memory cell formed on a memory cell forming region of a semiconductor substrate,
- said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode,
- an insulating film formed on the gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETs,
- a first conductive film formed on said insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, wherein a local wiring line is comprised of said first conductive film,
- a dielectric film formed on said first conductive film, and
- a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET,
- wherein said second conductive film extends over said first conductive film, and
- wherein a first capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film;
- and
- a second capacitor element formed on a peripheral circuit forming region of said semiconductor substrate,
- wherein said second capacitor element is comprised of same level conductive layers as said first conductive film and said second conductive film.
8 more elements
A semiconductor integrated circuit device, comprising:
- a memory cell formed on a first region of a semiconductor substrate,
- said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode,
- an insulating film formed on the gate electrodes of said first and second n-channel MISFETs, and said first and second p-channel MISFETs,
- a first conductive film formed on said insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, wherein a local wiring line is comprised of said first conductive film,
- a dielectric film formed on said first conductive film, and
- a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET,
- wherein said second conductive film extends over said first conductive film, and
- wherein a first capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film;
- and
- a second capacitor element formed on a second region of said semiconductor substrate,
- wherein said second capacitor element is comprised of same level conductive layers as said first conductive film and said second conductive film.
8 more elements
A semiconductor integrated circuit device, comprising:
- a memory cell formed on a memory cell forming region of a semiconductor substrate,
- said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode,
- an insulating film formed on the gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETs,
- a first conductive film formed on said insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
- a dielectric film formed on said first conductive film, and
- a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, said gate electrode of said firs t n-channel MISFET, and said gate electrode of said first p-channel MISFET,
- wherein said second conductive film extends over said first conductive film, and
- wherein a first capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film;
- and
- a second capacitor element formed on a peripheral circuit forming region of said semiconductor substrate,
- wherein said second capacitor element is comprised of same level conductive layers as said first conductive film and said second conductive film, and
- wherein said second capacitor element is included in an input/output protective circuit.
9 more elements
A semiconductor integrated circuit device, comprising:
- a memory cell formed on a first region of a semiconductor substrate,
- said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode,
- an insulating film formed on the gate electrodes of said first and second n-channel MISFETs, and said first and second p-channel MISFETs,
- a first conductive film formed on said insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
- a dielectric film formed on said first conductive film, and
- a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET,
- wherein said second conductive film extends over said first conductive film, and
- wherein a first capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film;
- and
- a second capacitor element formed on a second region of said semiconductor substrate,
- wherein said second capacitor element is comprised of same level conductive layers as said first conductive film and said second conductive film, and
- wherein said second capacitor element is included in an input/output protective circuit.
9 more elements
A semiconductor integrated circuit device comprising:
- a memory cell formed on a first region of a semiconductor substrate,
- said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET,
- an insulating film formed on gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETs,
- a first conductive film formed on said insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
- a dielectric film formed on said first conductive film,
- a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET,
- wherein said second conductive film extends over said first conductive film, and
- wherein a first capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film;
- and
- a second capacitor element included in a peripheral circuit and formed on a second region, of said semiconductor substrate, different from said first region,
- wherein said second capacitor element is comprised of same level conductive layers as said first conductive film and said second conductive film.
8 more elements
A semiconductor integrated circuit device comprising:
- a memory cell formed on a first region of a semiconductor substrate,
- said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET,
- an insulating film formed on gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETs,
- a first conductive film formed on said insulating film and being electrically connected to a drain region of said first n-channel MISFET, a drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET,
- a dielectric film formed on said first conductive film,
- a second conductive film formed on said dielectric film and being electrically connected to a drain region of said second n-channel MISFET, a drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET,
- wherein said second conductive film extends over said first conductive film, and
- wherein a first capacitor element is comprised of said first conductive film, said dielectric film, and said second conductive film;
- and
- a second capacitor element formed on a second region, of said semiconductor substrate, different from said first region where said memory cell is formed,
- wherein said second capacitor element is comprised of same level conductive layers as said first conductive film and said second conductive film.
8 more elements
Dependencies are inferred from the claim text.