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US 6,476,433 B1Granted
Semiconductor interconnection structure and method
AssigneeMicron Technology, Inc.
InventorsJeff Wu, Randhir P. S. Thakur
Life of this patent
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Abstract
A memory device and method in which the capacitor lower electrode within the memory cell array and a first interconnection layer within the peripheral circuitry are provided simultaneously from the same conductive material. The capacitor upper electrode and a second interconnection layer within the peripheral circuitry are also provided simultaneously from the same conductive material.
Claims17
A method of forming a DRAM, said method comprising the steps of:
- providing a memory cell array area and a peripheral circuit area on a semiconductor substrate,
- providing a first conductive layer in said peripheral circuit area and in said memory cell array area,
- patterning said first conductive layer as a capacitor lower electrode in said memory cell array area and as first interconnection layer in said peripheral circuit area,
- providing a dielectric layer over said first conductive layer within said memory cell array area and said peripheral circuit area, wherein at least a portion of said dielectric layer in said memory cell array is comprised of a high K dielectric and at least a portion of said dielectric layer in said peripheral circuit is comprised of a low K dielectric,
- providing a second conductive layer over said dielectric layer, and
- patterning said second conductive layer as a capacitor upper electrode in said memory cell array area and a second interconnection layer in said peripheral circuit area.
3 more elements
A method of electrically connecting a memory cell array to peripheral circuitry within a computer memory system, said method comprising the steps of:
- providing a memory cell array having at least one capacitor including an upper electrode layer and a lower electrode layer,
- providing a peripheral circuit area having first and second interconnection layers, wherein said first interconnection layer is deposited in the same step and formed of the same material as said lower electrode layer and said second interconnection layer is deposited in the same step and formed of the same material as said upper electrode layer,
- providing a first dielectric film between said upper and lower electrode layers, wherein said first dielectric film is comprised of a high K dielectric, and
- providing a second dielectric film between said first and second interconnection layers, wherein said second dielectric film is comprised of a low K dielectric.
1 more element
Dependencies are inferred from the claim text.