Structures and methods for enhancing capacitors in integrated circuits

A capacitor in a DRAM cell comprising:

• a first electrode;
• a dielectric coupled to the first electrode;
• a second electrode coupled to the dielectric;
• and
• a substantially homogeneous inhibiting layer adjoiningly coupled to and substantially enclosing the first electrode, the dielectric, and the second electrode, wherein the inhibiting layer inhibits dielectric degradation in the presence of contaminants.

A capacitor comprising:

• at least one substantially homogeneous inhibiting layer to inhibit dielectric degradation in the presence of contaminants, wherein the at least one inhibiting layer defines an exposed surface and at least two sidewalls that extend from the surface;
• a first conductive layer on the at least one inhibiting layer;
• a dielectric layer on the first conductive layer;
• and
• a second conductive layer on the dielectric layer, the at least one substantially homogeneous inhibiting layer substantially enclosing the first conductive layer, the dielectric layer, and the second conductive layer except at the surface.

A capacitor comprising:

• at least one substantially homogeneous inhibiting layer to inhibit dielectric degradation in the presence of contaminants, wherein the at least one inhibiting layer defines an aperture and at least two sidewalls that extend outwardly from the aperture;
• a first conductive layer having a first and second surface, wherein the first surface of the first conductive layer adjoins the at least one inhibiting layer such that the aperture of the at least one inhibiting layer exposes a portion of the first surface of the first conductive layer;
• a dielectric layer on the first conductive layer;
• and
• a second conductive layer on the dielectric layer, the at least one substantially homogeneous inhibiting layer substantially enclosing the first conductive layer, the dielectric layer, and the second conductive layer except at the aperture.

A capacitor comprising:

• at least one substantially homogeneous inhibiting layer to inhibit dielectric degradation in the presence of contaminants, wherein the at least one inhibiting layer defines an aperture and at least two sidewalls that extend outwardly from the aperture;
• a first conductive layer having a first and second surface, wherein the first surface of the first conductive layer adjoins the at least one substantially homogeneous inhibiting layer such that the aperture of the at least one substantially homogeneous inhibiting layer exposes a portion of the first surface of the first conductive layer;
• a dielectric layer having a first surface and a second surface, wherein the first surface of the dielectric layer adjoins the second surface of the first conductive layer, and wherein the first surface of the dielectric layer adjoins a portion of the at least two sidewalls of the at least one substantially homogeneous inhibiting layer to terminate at the first and second terminals;
• and
• a second conductive layer on the dielectric layer, the at least one substantially homogeneous inhibiting layer substantially enclosing the first conductive layer except at the aperture, the dielectric layer, and the second conductive layer.

A capacitor comprising:

• at least one substantially homogeneous inhibiting layer to inhibit dielectric degradation in the presence of contaminants, wherein the at least one substantially homogeneous inhibiting layer defines an aperture and at least two sidewalls that extend outwardly from the aperture;
• a first conductive layer having a first and second surface, wherein the first surface of the first conductive layer adjoins the at least one inhibiting layer such that the aperture of the at least one substantially homogeneous inhibiting layer exposes a portion of the first surface of the first conductive layer;
• a dielectric layer having a first surface and a second surface, wherein the first surface of the dielectric layer adjoins the second surface of the first conductive layer, and wherein the first surface of the dielectric layer adjoins a portion of the at least two sidewalls of the at least one substantially homogeneous inhibiting layer;
• and
• a second conductive layer having a first surface and a second surface, wherein the first surface of the second conductive layer adjoins the second surface of the dielectric layer, the at least one substantially homogeneous inhibiting layer substantially enclosing the first conductive layer except at the aperture, the dielectric layer, and the second conductive layer.

A capacitor comprising:

• a first and second inhibiting layers, wherein the first inhibiting layer defines a cylindrical chamber having an aperture and at least two sidewalls that extend outwardly from the aperture to terminate at a first and second terminals;
• a first conductive layer adjoiningly coupled to the first inhibiting layer such that the aperture of the first inhibiting layer exposes a portion of the first conductive layer;
• a dielectric layer adjoiningly coupled to the first conductive layer and a portion of the at least two sidewalls of the first inhibiting layer to terminate at the first and second terminals;
• a second conductive layer adjoiningly coupled to the dielectric layer to terminate at the first and second terminals;
• and
• wherein the second inhibiting layer adjoiningly coupled to the second conductive layer to terminate at the first and second terminals.

A capacitor comprising:

• a first inhibiting layer, wherein the first inhibiting layer defines a cylindrical chamber having an aperture and at least two sidewalls that extend outwardly from the aperture to terminate at a first and second terminals;
• a first conductive layer adjoiningly coupled to the first inhibiting layer such that the aperture of the first inhibiting layer exposes a portion of the first conductive layer;
• a dielectric layer adjoiningly coupled to the first conductive layer and a portion of the at least two sidewalls of the first inhibiting layer to terminate at the first and second terminals;
• a second conductive layer adjoiningly coupled to the dielectric layer to terminate at the first and second terminals;
• a second inhibiting layer adjoiningly coupled to the second conductive layer to terminate at the first and second terminals;
• and
• a third inhibiting layer abuttingly coupled to the first inhibiting layer, the first conductive layer, the dielectric layer, the second conductive layer, and the second inhibiting layer at the first and second terminals.

A semiconductor structure comprising:

• an insulator layer;
• a first substantially homogeneous inhibiting layer to inhibit dielectric degradation in the presence of contaminants, wherein the first substantially homogeneous inhibiting layer is adjoiningly disposed to the insulator layer such that the first substantially homogeneous inhibiting layer defines in the insulator layer a cylindrical chamber having an aperture and at least two sidewalls that extend outwardly from the aperture;
• a first conductive layer adjoiningly coupled to the first inhibiting layer such that the aperture of the first substantially homogeneous inhibiting layer exposes a portion of the first conductive layer;
• a dielectric layer adjoiningly coupled to the first conductive layer and a portion of the at least two sidewalls of the first substantially homogeneous inhibiting layer;
• and
• a second conductive layer adjoiningly coupled to the dielectric layer, the first substantially homogeneous inhibiting layer substantially enclosing the first conductive layer except at the aperture, the dielectric layer, and the second conductive layer.

A capacitor in a dynamic random access memory cell comprising:

• a first electrode;
• a dielectric coupled to the first electrode, wherein the dielectric includes a thin film dielectric, wherein the dielectric includes an oxide compound, wherein the oxide compound includes barium strontium titanate;
• a second electrode coupled to the dielectric;
• and
• at least one substantially homogeneous inhibiting layer that couples to and substantially encloses the first electrode, the dielectric, and the second electrode to define a chamber, wherein the at least one substantially homogeneous inhibiting layer is selected from a group consisting of a nitride compound, an oxynitride compound, and an oxide compound, wherein the nitride compound includes SixNy, wherein the oxynitride compound includes a molecular formula of SiOxNy, wherein the oxide compound includes Al2O3 and (SrRu)O3, and wherein x and y are indicative of a desired number of atoms.

A memory cell comprising:

• a capacitor that includes:
• a first electrode;
• a dielectric coupled to the first electrode, wherein the dielectric includes a thin film dielectric, wherein the dielectric includes an oxide compound, wherein the oxide compound includes barium strontium titanate;
• a second electrode coupled to the dielectric;
• and
• at least one substantially homogeneous inhibiting layer that couples to and substantially encloses the first electrode, the dielectric, and the second electrode to define a chamber, wherein the at least one substantially homogeneous inhibiting layer includes a compound selected from a group consisting of a nitride compound, an oxynitride compound, and an oxide compound, wherein the nitride compound includes SixNy, wherein the oxynitride compound includes a molecular formula of SiOxNy, wherein the oxide compound includes Al2O3 and (SrRu)O3, and wherein x and y are indicative of a desired number of atoms;
• and
• at least one transistor having a gate, drain, and source, wherein the drain is coupled to the the first electrode.

A memory array comprising:

• at least one capacitor that includes:
• a first electrode;
• a dielectric coupled to the first electrode, wherein the dielectric includes a thin film dielectric, wherein the dielectric includes an oxide compound, wherein the oxide compound includes barium strontium titanate;
• a second electrode coupled to the dielectric;
• at least one substantially homogeneous inhibiting layer that couples to and substantially encloses the first electrode, the dielectric, and the second electrode to define a chamber, wherein the at least one substantially homogeneous inhibiting layer includes a compound selected from a group consisting of a nitride compound, an oxynitride compound, and an oxide compound, wherein the nitride compound includes SixNy, wherein the oxynitride compound includes a molecular formula of SiOxNy, wherein the oxide compound includes Al2O3 and (SrRu)O3, and wherein x and y are indicative of a desired number of atoms;
• and
• at least one transistor having a gate, drain, and source, wherein the drain is coupled to the the first electrode.

A memory device comprising:

• an array of memory cells, wherein the array includes at least one capacitor that includes:
• a first electrode;
• a dielectric coupled to the first electrode, wherein the dielectric includes a thin film dielectric, wherein the dielectric includes an oxide compound, wherein the oxide compound includes barium strontium titanate;
• a second electrode coupled to the dielectric;
• and
• at least one substantially homogeneous inhibiting layer that couples to and substantially encloses the first electrode, the dielectric, and the second electrode to define a chamber, wherein the at least one substantially homogeneous inhibiting layer includes a compound selected from a group consisting of a nitride compound, an oxynitride compound, and an oxide compound, wherein the nitride compound includes SixNy, wherein the oxynitride compound includes a molecular formula of SiOxNy, wherein the oxide compound includes Al2O3 and (SrRu)O3, and wherein x and y are indicative of a desired number of atoms;
• at least one transistor having a gate, drain, and source, wherein the drain is coupled to the the first electrode;
• an address decoder;
• a row access circuitry;
• a column access circuitry;
• a controller;
• and
• an input/output circuit.

A circuit module comprising:

• a plurality of dies, wherein at least one die includes at least one array of memory cells, wherein the array includes at least one capacitor that includes:
• a first electrode;
• a dielectric coupled to the first electrode, wherein the dielectric includes a thin film dielectric, wherein the dielectric includes an oxide compound, wherein the oxide compound includes barium strontium titanate;
• a second electrode coupled to the dielectric;
• and
• at least one substantially homogeneous inhibiting layer that couples to and substantially encloses the first electrode, the dielectric, and the second electrode to define a chamber, wherein the at least one substantially homogeneous inhibiting layer includes a compound selected from a group consisting of a nitride compound, an oxynitride compound, and an oxide compound, wherein the nitride compound includes SixNy, wherein the oxynitride compound includes a molecular formula of SiOxNy, wherein the oxide compound includes Al2O3and (SrRu)O3, and wherein x and y are indicative of a desired number of atoms;
• at least one transistor having a gate, drain, and source, wherein the drain is coupled to the the first electrode;
• and
• a plurality of leads coupled to the plurality of dies to provide unilateral or bilateral communication and control.

A memory module comprising:

• a plurality of memory devices, wherein at least one memory device includes at least one array of memory cells, wherein the array includes at least one capacitor that includes:
• a first electrode;
• a dielectric coupled to the first electrode, wherein the dielectric includes a thin film dielectric, wherein the dielectric includes an oxide compound, wherein the oxide compound includes barium strontium titanate;
• a second electrode coupled to the dielectric;
• and
• at least one substantially homogeneous inhibiting layer that couples to and substantially encloses the first electrode, the dielectric, and the second electrode to define a chamber, wherein the at least one substantially homogeneous inhibiting layer includes a compound selected from a group consisting of a nitride compound, an oxynitride compound, and an oxide compound, wherein the nitride compound includes SixNy, wherein the oxynitride compound includes a molecular formula of SiOxNy, wherein the oxide compound includes Al2O3 and (SrRu)O3, and wherein x and y are indicative of a desired number of atoms;
• at least one transistor having a gate, drain, and source, wherein the drain is coupled to the the first electrode;
• a plurality of command links coupled to the plurality of memory devices to communicate at least one command signal;
• and
• a plurality of data links coupled to the plurality of memory devices to communicate data.

An electronic system comprising:

• a plurality of circuit modules includes a plurality of dies, wherein at least one die includes at least one array of memory cells, wherein the array comprises at least one capacitor that includes:
• a first electrode;
• a dielectric coupled to the first electrode, wherein the dielectric includes a thin film dielectric, wherein the dielectric includes an oxide compound, wherein the oxide compound includes barium strontium titanate;
• a second electrode coupled to the dielectric;
• and
• at least one substantially homogeneous inhibiting layer that couples to and substantially encloses the first electrode, the dielectric, and the second electrode to define a chamber, wherein the at least one substantially homogeneous inhibiting layer includes a compound selected from a group consisting of a nitride compound, an oxynitride compound, and an oxide compound, wherein the nitride compound includes SixNy, wherein the oxynitride compound includes a molecular formula of SiOxNy, wherein the oxide compound includes Al2O3 and (SrRu)O3, and wherein x and y are indicative of a desired number of atoms;
• at least one transistor having a gate, drain, and source, wherein the drain is coupled to the the first electrode;
• a plurality of leads coupled to the plurality of dies to provide unilateral or bilateral communication and control;
• and
• a user interface.

A memory system comprising:

• a plurality of memory modules includes a plurality of memory devices, wherein at least one memory device includes at least one array of memory cells, wherein the array comprises at least one capacitor that includes:
• a first electrode;
• a dielectric coupled to the first electrode, wherein the dielectric includes a thin film dielectric, wherein the dielectric includes an oxide compound, wherein the oxide compound includes barium strontium titanate;
• a second electrode coupled to the dielectric;
• and
• at least one substantially homogeneous inhibiting layer that couples to and substantially encloses the first electrode, the dielectric, and the second electrode to define a chamber, wherein the at least one substantially homogeneous inhibiting layer includes a compound selected from a group consisting of a nitride compound, an oxynitride compound, and an oxide compound, wherein the nitride compound includes SixNy, wherein the oxynitride compound includes a molecular formula of SiOxNy, wherein the oxide compound includes Al2O3 and (SrRu)O3, and wherein x and y are indicative of a desired number of atoms;
• at least one transistor having a gate, drain, and source, wherein the drain is coupled to the the first electrode;
• a plurality of command links coupled to the plurality of memory devices to communicate at least one command signal;
• a plurality of data links coupled to the plurality of memory devices to communicate data;
• and
• a memory controller.

A computer system comprising:

• a processor;
• a memory system that comprises a plurality of memory modules, wherein one of the plurality of memory modules comprises a plurality of memory devices, wherein at least one memory device comprises at least one array of memory cells, wherein the array comprises at least one capacitor that includes:
• a first electrode;
• a dielectric coupled to the first electrode, wherein the dielectric includes a thin film dielectric, wherein the dielectric includes an oxide compound, wherein the oxide compound includes barium strontium titanate;
• a second electrode coupled to the dielectric;
• and
• at least one substantially homogeneous inhibiting layer that couples to and substantially encloses the first electrode, the dielectric, and the second electrode to define a chamber, wherein the at least one substantially homogeneous inhibiting layer includes a compound selected from a group consisting of a nitride compound, an oxynitride compound, and an oxide compound, wherein the nitride compound includes SixNy, wherein the oxynitride compound includes a molecular formula of SiOxNy, wherein the oxide compound includes Al2O3 and (SrRu)O3, and wherein x and y are indicative of a desired number of atoms;
• and
• at least one transistor having a gate, drain, and source, wherein the drain is coupled to the the first electrode;
• a plurality of command links coupled to the plurality of memory devices to communicate at least one command signal;
• a plurality of data links coupled to the plurality of memory devices to communicate data;
• a memory controller;
• at least one user interface device, wherein the at least one user interface device includes a monitor;
• at least one output device, wherein the at least one output device includes a printer;
• and
• at least one bulk storage device.