Semiconductor device with breakdown voltage improved by hetero region
AssigneeKabushiki Kaisha Toshiba
InventorYoshiro Baba
Life of this patent
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Abstract
A power MOSFET includes an n−-drain layer, a drain contact layer disposed on a first side of the drain layer, a p-type base layer disposed on a second side of the drain layer, and an n-source layer disposed on the base layer. A gate electrode faces, through a gate insulating film, a channel region, which is part of the base layer between the drain and source layers. Source and drain electrodes are electrically connected to the source and drain contact layers, respectively. A plurality of hetero regions having a dielectric constant higher than that of the drain layer is disposed in the drain layer between the source and drain electrodes.
Claims20
A semiconductor device comprising:
- a first semiconductor layer of a first conductivity type;
- a second semiconductor layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer, and disposed on the first semiconductor layer;
- a third semiconductor layer of a second conductivity type, formed in a surface of the second semiconductor layer on a side reverse to the first semiconductor layer;
- a fourth semiconductor layer of the first conductivity type formed in a surface of the third semiconductor layer;
- a gate electrode facing, through a gate insulating film, a surface of the third semiconductor layer between the second and fourth semiconductor layers;
- a first electrode electrically connected to the fourth semiconductor layer;
- a second electrode electrically connected to the first semiconductor layer, such that the second semiconductor layer is sandwiched between the first and second electrodes;
- and
- a plurality of hetero regions having a dielectric constant higher than that of the second semiconductor layer, and disposed in the second semiconductor layer at positions located between the second electrode and a pn junction between the second and third semiconductor layers, and out of contact with the pn junction.
A MISFET comprising:
- a drain layer of a first conductivity type having first and second sides reverse to each other;
- a base layer of a second conductivity type disposed on the drain layer on the first side;
- a source layer of a first conductivity type disposed on the base layer;
- a gate electrode facing, through a gate insulating film, a channel region, which is part of the base layer between the drain and source layers;
- a source electrode electrically connected to the source layer;
- a drain electrode electrically connected to the drain layer on the second side, such that the drain layer is sandwiched between the source and drain electrodes;
- and
- a plurality of hereto regions having a dielectric constant higher than that of the drain layer, and disposed in the drain layer at positions located between the drain electrode and a pn junction between the drain layer and the base layer, and out of contact with the pn junction, the hetero regions being arranged to lower an electric field in the drain layer when a reverse bias is applied between the source and drain electrodes, thereby improving a breakdown voltage of the MISFET, as compared to a case where no hetero regions are formed.
Dependencies are inferred from the claim text.