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AssigneeAlcatel
InventorJoannes Mathilda Josephus Sevenhans
Estimating the term…
The field effect transistor includes a control terminal (G), a first main terminal (S) and a second main terminal (D1). The control terminal (G) is included to be coupled to gate voltage means which are adapted to provide a control voltage (Vg) which controls a flow of carriers (e) flowing from the first main terminal (S) to the second main terminal (D1). The field effect transistor further includes a third main terminal (D2) which is positioned and adapted in order to enable a high input resistance control current means (CS), which is coupled to the third main terminal (D2), to deviate part (e′) of the flow of carriers from the first main terminal (S) to the third main terminal (D2). The third main terminal is called the double drain (D2) of the field effect transistor.
A field effect transistor comprising:
A control method for controlling a field effect transistor which includes a control terminal, a first main terminal, a second main terminal and a double drain terminal, said control method comprising the steps of:
A frequency mixer means comprising at least one field effect transistor, said field effect transistor comprising:
Dependencies are inferred from the claim text.