US 6,475,917 B1 · Method to reduce the metal TiN ARC damage in etching back process

Abstract

A method for forming on a substrate employed within a microelectronics fabrication a planarized inter-level metal dielectric (IMD) layer employing spin-on-glass (SOG) dielectric material, with attenuated etching damage to underlying layers. There is provided a substrate upon which is formed a patterned microelectronics layer over which is formed an inter-level metal dielectric (IMD) layer comprising a first silicon oxide dielectric layer and a second spin-on-glass (SOG) dielectric layer. The IMD layer is then planarized by plasma etchback method employing an etch cycle interrupted by an inert gas flushing step and substrate backside cooling by helium gas to control substrate temperature and etching reaction rates, resulting in attenuated damage to underlying layers resulting from over-etching of the IMD layer.

Claims16

Dependent claims

A method for forming upon a substrate employed within a microelectronics fabrication an inter-level metal dielectric (IMD) layer which is planarized with attenuated damage to underlying layers comprising:

providing a substrate;
forming upon the substrate a patterned microelectronics layer;
forming over the substrate an inter-level metal dielectric (IMD) layer further comprising:
a first silicon oxide dielectric layer;
a second dielectric layer formed employing spin-on-glass (SOG) dielectric material;
and
planarizing the surface of the inter-level metal dielectric (IMD) layer employing plasma etch back method, wherein the patterned microelectronics layer is formed of material having a greater negative temperature coefficient of etching reaction rate by the plasma etch back method than that of the silicon oxide dielectric material, and wherein the SOG dielectric material is selectively etched at a greater rate than is the silicon oxide dielectric material and the patterned microelectronics layer material.

4 more elements

A method for forming upon a semiconductor substrate, with varying topography and circuit density employed within an integrated circuit microelectronics fabrication, an inter-level metal dielectric (IMD) layer which is planarized with attenuated damage to underlying conductor layer comprising:

providing a semiconductor substrate;
forming over the semiconductor substrate a first series of conductor lines and a second contiguous series of conductor lines which constitute together a patterned microelectronics conductor layer;
forming over the substrate a first silicon oxide dielectric layer;
forming over the substrate a second dielectric layer employing a spin-on-glass (SOG) low dielectric constant dielectric material to complete the inter-level metal dielectric (IMD) layer;
and
planarizing the surface of the IMD layer employing plasma etch back method, wherein the patterned microelectronics layer is formed of material having a greater negative temperature coefficient of etching reaction rate by the plasma etch back method than that of the silicon oxide dielectric material, and wherein the SOG dielectric material is selectively etched at a greater rate than is the silicon oxide dielectric material and the patterned microelectronics layer material.

3 more elements

Dependencies are inferred from the claim text.

Method to reduce the metal TiN ARC damage in etching back process

Life of this patent

Method to reduce the metal TiN ARC damage in etching back process

Life of this patent

Abstract

Claims16