Method of patterning gate electrode with ultra-thin gate dielectric

A method of creating ultra-thin layers of gate oxide underlying polysilicon gate structures, comprising the steps of:

• providing a semiconductor substrate said substrate having been provided with Shallow Trench Isolation regions in its surface whereby a layer of sacrificial gate oxide has been deposited on a surface of said substrate including a surface of said STI regions to a thickness between about 100 and 200 Angstrom whereby furthermore a channel implant has been performed into a surface of said substrate;
• depositing a layer of nitride over a surface of said layer of sacrificial gate oxide to a thickness between about 2000 and 3000 Angstrom;
• patterning and etching said layer of nitride whereby said patterning and etching creates openings in said layer of nitride that align with surface areas in said layer of sacrificial gate oxide where said ultra-thin layers of gate oxide are to be created thereby exposing said layer of said sacrificial gate oxide in said surface areas said etching of nitride being an anisotropic etch that is selective to the underlying layer of sacrificial oxide, allowing for an over-etch into the surface of the layer of sacrificial oxide;
• pre-cleaning said exposed surface of said layer of sacrificial gate oxide where said ultra-thin layers of gate oxide are to be created thereby creating pre-cleaned areas where said ultra-thin layers of gate oxide are to be created;
• performing gate oxide growth over said pre-cleaned areas thereby creating said ultra-thin layers of gate oxide;
• depositing a layer of polysilicon over a surface of said layer of nitride to a thickness between about 3000 and 4000 Angstrom thereby including a surface area of said ultra-thin layers of gate oxide;
• removing said layer of polysilicon from a surface of said layer of nitride thereby leaving said poly inside said openings in said layer of nitride said removal to apply methods of polysilicon CMP either with or without aid of reverse mask said removal of said layer of polysilicon to proceed to a point where the thickness of said layer of nitride has been reduced from between about 2000 and 3000 Angstrom to between about 1500 and 2500 Angstrom thereby forming a polysilicon gate structure that overlies said ultra-thin layers of gate oxide;
• and
• removing said layer of nitride from a surface of said layer of sacrificial gate oxide using an isotropic phosphoric wet etch thereby leaving said polysilicon gate structure in place.

A method of creating ultra-thin layers of gate oxide whereby said ultra-thin layers of gate oxide serve as a gate oxide of a polysilicon gate structure, comprising the steps of:

• providing a semiconductor substrate wherein said semiconductor substrate comprises an active region that is laterally displaced between a pair of isolation regions;
• growing a layer of sacrificial gate oxide on a surface of said substrate to a thickness of between about 150 and 250 Angstrom;
• performing channel implant into a surface of said substrate;
• depositing a layer of nitride over a surface of said layer of gate oxide to a thickness of between about 2000 and 3000 Angstrom;
• depositing a layer of tetra-ethyl-ortho-silicate (TEOS) oxide on a surface of said layer of nitride to a thickness of between about 200 and 300 Angstrom;
• patterning and etching said layer of TEOS oxide and said layer of nitride thereby creating openings in said layer of TEOS oxide and said layer of nitride thereby furthermore exposing a surface areas of said layer of sacrificial gate oxide where said ultra-thin layers of gate oxide are to be created, allowing for an over-etch into the surface of the layer of sacrificial oxide;
• depositing a thin conformal layer of nitride over a surface of said layer of TEOS oxide to a thickness between about 200 and 300 Angstrom thereby including said created openings in said layer of TEOS oxide and said layer of nitride;
• isotropically etching said thin conformal layer of nitride thereby removing said conformal layer of nitride from a surface of said layer of TEOS oxide thereby furthermore forming thin sidewall spacers on sidewalls of said openings in said layer of TEOS oxide and said layer of nitride said etch to be selective to oxide thereby furthermore exposing a surface of said layer of sacrificial gate oxide where said ultra-thin layers of gate oxide are to be created;
• pre-cleaning said exposed surface of said layer of sacrificial gate oxide where said ultra-thin layers of gate oxide are to be created thereby creating pre-cleaned areas where said ultra-thin layers of gate oxide are to be created said pre-cleaning to remove said TEOS oxide from the surface of said layer of nitride said pre-cleaning furthermore removing said sacrificial oxide from surface areas where said ultra-thin layers of gate oxide are to be created;
• performing gate oxide growth over said pre-cleaned areas thereby creating said ultra-thin layers of gate oxide;
• depositing a layer of polysilicon over a surface of said layer of nitride thereby including said openings in said layer of nitride said layer of polysilicon thereby overlaying said ultra-thin layers of gate oxide;
• removing said layer of polysilicon from a surface of said layer of nitride thereby leaving said deposited polysilicon inside said openings in said layer of nitride thereby creating poly gate structures that overly said ultra-thin layers of gate oxide;
• and
• removing said layer of nitride thereby leaving said poly gate structures in place.

A method of creating ultra-thin layers of gate oxide underlying polysilicon gate structures, comprising the steps of:

• providing a semiconductor substrate said substrate having been provided with Shallow Trench Isolation regions in its surface whereby a layer of sacrificial gate oxide has been deposited on a surface of said substrate including a surface of said STI regions to a thickness between about 150 and 250 Angstrom whereby furthermore a channel implant has been performed into a surface of said substrate;
• depositing a layer of nitride over a surface of said layer of sacrificial gate oxide to a thickness between about 2000 and 3000 Angstrom;
• depositing a layer of TEOS oxide over a surface of said layer of nitride to a thickness of between about 200 and 300 Angstrom;
• patterning and etching said layer of TEOS oxide and said layer of nitride whereby said patterning and etching creates openings in said layers of TEOS nitride and said layer of nitride that align with surface areas in said layer of sacrificial gate oxide where said ultra-thin layers of gate oxide are to be created thereby exposing said layer of said sacrificial gate oxide in said surface areas said etching of TEOS oxide being an anisotropic etch said etching of nitride being an anisotropic etch that is selective to the underlying layer of sacrificial oxide, allowing for an over-etch into the surface of the layer of sacrificial oxide;
• depositing a thin conformal layer of nitride over a surface of said layer of TEOS to a thickness between about 200 and 300 Angstrom thereby including said openings that have been created in said layer of TEOS oxide and said layer of nitride;
• isotropically etching said thin conformal layer of nitride thereby forming thin sidewall spacers on sidewalls of said openings in said layer of TEOS oxide and layer of nitride;
• pre-cleaning said exposed surface of said layer of sacrificial gate oxide where said ultra-thin layers of gate oxide are to be created thereby creating pre-cleaned areas where said ultra-thin layers of gate oxide are to be created said pre-cleaning to remove said TEOS oxide from the surface of said layer of nitride and from the surface where said ultra-thin layers of gate oxide are to be created;
• performing gate oxide growth over said pre-cleaned areas thereby creating said ultra-thin layers of gate oxide;
• depositing a layer of polysilicon over a surface of said layer of nitride to a thickness between about 3000 and 4000 Angstrom thereby including the surface area of said ultra-thin layers of gate oxide;
• removing said layer of polysilicon from a surface of said layer of nitride thereby leaving said poly inside said openings in said layer of nitride said removal to apply methods of polysilicon CMP either with or without aid of reverse mask said removal of said layer of polysilicon to proceed to a point where the thickness of said layer of nitride has been reduced from between about 2000 and 3000 Angstrom to between about 1500 and 2500 Angstrom thereby forming a polysilicon gate structure that overlies said ultra-thin layers of gate oxide;
• and
• removing said layer of nitride from a surface of said layer of sacrificial gate oxide using an isotropic phosphoric wet etch thereby leaving said polysilicon gate structure in place.