Gate contact etch sequence and plasma doping method for sub-150 NM DT-based DRAM devices

A method of forming contacts in the fabrication of a DRAM integrated circuit comprising:

• providing semiconductor device structures in and on a substrate wherein said substrate is divided into an array area and a periphery area;
• covering said semiconductor device structures with a dielectric layer;
• concurrently etching through said dielectric layer in said array area to form bit line contact openings and etching through said dielectric layer in said periphery area to form substrate contact openings;
• forming doped regions in said substrate exposed within said bit line contact openings and said substrate contact openings using a plasma doping process;
• thereafter etching through said dielectric layer to form a gate contact opening;
• and
• filling said bit line contact openings, said substrate contact openings, and said gate contact opening with a conducting layer to complete said forming contacts in the fabrication of said DRAM integrated circuit device.

A method of forming contacts in the fabrication of a DRAM integrated circuit comprising:

• providing semiconductor device structures in and on a substrate wherein-said substrate is divided into an array area and a periphery area;
• covering said semiconductor device structures with a dielectric layer;
• concurrently etching through said dielectric layer in said array area to form bit line contact openings and etching through said dielectric layer in said periphery area to form substrate contact openings using a self-aligned contact etching process;
• forming doped regions in said substrate exposed within said bit line contact openings and said substrate contact openings using a plasma doping process;
• thereafter etching through said dielectric layer to form a gate contact opening;
• and
• filling said bit line contact openings, said substrate contact openings, and said gate contact opening with a conducting layer to complete said forming contacts in the fabrication of said DRAM integrated circuit device.