Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques
AssigneeAdvanced Micro Devices, Inc.
InventorsUzodinma Okoroanyanwu, Ramkumar Subramanian
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Abstract
A damascene structure and method of making the same in a low k dielectric material employs an imageable layer in which the damascene pattern is provided. The imageable layer is an alicyclic polymer into which silicon is incorporated by liquid silylation, for example. The silicon-rich regions are converted upon exposure to the plasma etch that etches the low k dielectric material into a hard mask containing silicon dioxide, for example. The low k dielectric material is protected from further etching by the mask thus created.
Claims17
A method of forming a damascene structure in a semiconductor device, comprising the steps of:
- forming a first low k dielectric layer;
- depositing an imageable layer comprising an alicyclic polymer on the first low k dielectric layer;
- patterning the first imageable layer to create a first patterned layer having an upper surface with an opening defined by side surfaces in the first patterned layer;
- performing liquid silylation of the first patterned layer to form a silicon-rich region on the upper surface and the side surfaces of the first patterned layer;
- etching the first low k dielectric layer through the opening while simultaneously converting the silicon-rich region into silicon dioxide which functions as a hard mask protecting the first low k dielectric layer from being etched except through the opening.
A method of forming a dual damascene structure in a semiconductor device, comprising the steps of:
- depositing a first imageable layer comprising an alicyclic polymer on a first low k dielectric layer;
- patterning the first imageable layer to create a first patterned layer having an upper surface and a via opening defined by side surfaces in the first patterned layer;
- performing liquid silylation the first patterned layer to form a silicon-rich region on the upper surface and side surface of the first patterned layer;
- forming a second low k dielectric layer on the first patterned layer;
- depositing a second imageable layer comprising an alicyclic polymer on the second low k dielectric layer;
- patterning the second imageable layer to create a second patterned layer having an upper surface and a trench defined by side surfaces in the second patterned layer, with at least a portion of the trench opening overlaying the via opening;
- performing liquid silylation of the second patterned layer to form a silicon-rich region on the upper surface and side surface of the second patterned layer;
- and
- etching the first and second low k dielectric layers through the trench opening and the via opening, while simultaneously transferring the silicon-rich regions on the first and second layers into the hard mask regions protecting the underlying low k dielectric layer.
Dependencies are inferred from the claim text.