Low capacitance wiring layout and method for making same
AssigneeMicron Technology, Inc.
InventorPaul A. Farrar
Life of this patent
Estimating the term…
Abstract
Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.
Claims8
A method for fabricating an integrated circuit having a plurality of wiring planes, each said plane including a plurality of wiring channels, said method comprising:
- providing a first layer of insulator material;
- providing a first plurality of wires on said first layer of insulator material;
- providing a second layer of insulator material over said first layer of insulator material;
- and
- providing a second plurality of wires on said second layer of insulator material, wherein said second plurality of wires extend in the same direction as said first plurality of wires and are each offset from said first plurality of wires, and wherein said first and second pluralities of wires are in separate planes.
A method for fabricating an integrated circuit having a plurality of wiring planes, each said plane including a plurality of wiring channels, said method comprising:
- providing a first layer of insulator material;
- masking said first layer of insulator material and etching a first plurality of said wiring channels therein in a first direction;
- filling said first plurality of wiring channels with conductive material;
- providing a second layer of insulator material over said first layer of insulator material;
- masking said second layer of insulator material and etching a second plurality of said wiring channels therein in said first direction, wherein said first plurality of said wiring channels is separated from said second plurality of said wiring channels by a portion of said second layer of insulator material;
- and
- filling said second plurality of wiring channels with conductive material, wherein said second plurality of wiring channels are each offset from said first plurality of wiring channels.
Dependencies are inferred from the claim text.