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AssigneeFuji Electric Co., Ltd.
InventorsTakahiro Sato, Katsunori Ueno, Tatsuhiko Fujihira, Kenji Kunihara, Yasuhiko Onishi, Susumu Iwamoto
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A method of manufacturing reduces costs and provides an excellent mass-productivity, super-junction semiconductor device, which facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double difflusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, the oxide film is removed by ion etching, and trenches are dug. The p-type epitaxial layers are buried in the trenches by selective epitaxial growth, and the remaining oxide film is removed. The portions of n-type semiconductor substrate not etched off remain as n-type drift regions, resulting in an alternating conductivity type layer formed of n-type drift regions and p-type partition regions. A drain electrode is deposited on the back surface of alternating conductivity type layer.
A method of manufacturing a semiconductor device, said semiconductor device including a semiconductor chip having a first major surface, a second major surface facing opposite to said first major surface, a device structure in the first major surface, and an alternating conductivity type layer between said first major surface and said second major surface, said alternating conductivity type layer being formed of first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type, said first semiconductor regions and said second semiconductor regions being arranged alternately with each other, said method comprising:
The method according to claim 9, wherein the impurity concentration in said first semiconductor regions or said second semiconductor regions is 1×1018 cm3 or higher.
A method of manufacturing a semiconductor device including an alternating conductivity type layer, said semiconductor device including a first semiconductor chip having a first major surface, and a device structure in said first major surface, and a second semiconductor chip having at least a part of said alternating conductivity type layer, said alternating conductivity type layer being formed of first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type, said first semiconductor regions and said second semiconductor regions being arranged alternately with each other, said method comprising:
Dependencies are inferred from the claim text.